| From 3ade04a214368610e514d4be375695ea12cdfc5f Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 21 Oct 2025 11:08:13 +0200 |
| Subject: drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji |
| |
| From: John Smith <itistotalbotnet@gmail.com> |
| |
| [ Upstream commit 07a13f913c291d6ec72ee4fc848d13ecfdc0e705 ] |
| |
| Previously this was initialized with zero which represented PCIe Gen |
| 1.0 instead of using the |
| maximum value from the speed table which is the behaviour of all other |
| smumgr implementations. |
| |
| Fixes: 18edef19ea44 ("drm/amd/powerplay: implement fw image related smu interface for Fiji.") |
| Signed-off-by: John Smith <itistotalbotnet@gmail.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| (cherry picked from commit c52238c9fb414555c68340cd80e487d982c1921c) |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c |
| index ecb9ee46d6b35..6049edcaf6ce9 100644 |
| --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c |
| +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c |
| @@ -2026,7 +2026,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr) |
| table->VoltageResponseTime = 0; |
| table->PhaseResponseTime = 0; |
| table->MemoryThermThrottleEnable = 1; |
| - table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ |
| + table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); |
| table->PCIeGenInterval = 1; |
| table->VRConfig = 0; |
| |
| -- |
| 2.51.0 |
| |
