| From 4055990950a6040e39510e282f7623de3979b81e Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 25 Jan 2022 19:50:33 +0530 |
| Subject: arm64: errata: Add detection for TRBE invalid prohibited states |
| |
| From: Anshuman Khandual <anshuman.khandual@arm.com> |
| |
| [ Upstream commit 3bd94a8759de9b724b83a80942b0354acd7701eb ] |
| |
| TRBE implementations affected by Arm erratum #2038923 might get TRBE into |
| an inconsistent view on whether trace is prohibited within the CPU. As a |
| result, the trace buffer or trace buffer state might be corrupted. This |
| happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, |
| followed by just a single context synchronization event before execution |
| changes from a context, in which trace is prohibited to one where it isn't, |
| or vice versa. In these mentioned conditions, the view of whether trace is |
| prohibited is inconsistent between parts of the CPU, and the trace buffer |
| or the trace buffer state might be corrupted. This adds a new errata |
| ARM64_ERRATUM_2038923 in arm64 errata framework. |
| |
| Cc: Catalin Marinas <catalin.marinas@arm.com> |
| Cc: Will Deacon <will@kernel.org> |
| Cc: Mathieu Poirier <mathieu.poirier@linaro.org> |
| Cc: Suzuki Poulose <suzuki.poulose@arm.com> |
| Cc: coresight@lists.linaro.org |
| Cc: linux-doc@vger.kernel.org |
| Cc: linux-arm-kernel@lists.infradead.org |
| Cc: linux-kernel@vger.kernel.org |
| Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> |
| Acked-by: Catalin Marinas <catalin.marinas@arm.com> |
| Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> |
| Link: https://lore.kernel.org/r/1643120437-14352-4-git-send-email-anshuman.khandual@arm.com |
| Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| Documentation/arm64/silicon-errata.rst | 2 ++ |
| arch/arm64/Kconfig | 23 +++++++++++++++++++++++ |
| arch/arm64/kernel/cpu_errata.c | 9 +++++++++ |
| arch/arm64/tools/cpucaps | 1 + |
| 4 files changed, 35 insertions(+) |
| |
| diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst |
| index 401a6e86c5084..d5c6befc44eb8 100644 |
| --- a/Documentation/arm64/silicon-errata.rst |
| +++ b/Documentation/arm64/silicon-errata.rst |
| @@ -54,6 +54,8 @@ stable kernels. |
| +----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | |
| +----------------+-----------------+-----------------+-----------------------------+ |
| +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | |
| ++----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | |
| +----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | |
| diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig |
| index 30c07b0d6b5c9..2b75e8a9bf88c 100644 |
| --- a/arch/arm64/Kconfig |
| +++ b/arch/arm64/Kconfig |
| @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 |
| |
| If unsure, say Y. |
| |
| +config ARM64_ERRATUM_2038923 |
| + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" |
| + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in |
| + default y |
| + help |
| + This option adds the workaround for ARM Cortex-A510 erratum 2038923. |
| + |
| + Affected Cortex-A510 core might cause an inconsistent view on whether trace is |
| + prohibited within the CPU. As a result, the trace buffer or trace buffer state |
| + might be corrupted. This happens after TRBE buffer has been enabled by setting |
| + TRBLIMITR_EL1.E, followed by just a single context synchronization event before |
| + execution changes from a context, in which trace is prohibited to one where it |
| + isn't, or vice versa. In these mentioned conditions, the view of whether trace |
| + is prohibited is inconsistent between parts of the CPU, and the trace buffer or |
| + the trace buffer state might be corrupted. |
| + |
| + Work around this in the driver by preventing an inconsistent view of whether the |
| + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a |
| + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or |
| + two ISB instructions if no ERET is to take place. |
| + |
| + If unsure, say Y. |
| + |
| config CAVIUM_ERRATUM_22375 |
| bool "Cavium erratum 22375, 24313" |
| default y |
| diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c |
| index a5456dd9a33f5..a64bf132c6336 100644 |
| --- a/arch/arm64/kernel/cpu_errata.c |
| +++ b/arch/arm64/kernel/cpu_errata.c |
| @@ -609,6 +609,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { |
| ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) |
| }, |
| #endif |
| +#ifdef CONFIG_ARM64_ERRATUM_2038923 |
| + { |
| + .desc = "ARM erratum 2038923", |
| + .capability = ARM64_WORKAROUND_2038923, |
| + |
| + /* Cortex-A510 r0p0 - r0p2 */ |
| + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) |
| + }, |
| +#endif |
| { |
| } |
| }; |
| diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps |
| index fca3cb329e1db..45a06d36d0807 100644 |
| --- a/arch/arm64/tools/cpucaps |
| +++ b/arch/arm64/tools/cpucaps |
| @@ -56,6 +56,7 @@ WORKAROUND_1463225 |
| WORKAROUND_1508412 |
| WORKAROUND_1542419 |
| WORKAROUND_2064142 |
| +WORKAROUND_2038923 |
| WORKAROUND_TRBE_OVERWRITE_FILL_MODE |
| WORKAROUND_TSB_FLUSH_FAILURE |
| WORKAROUND_TRBE_WRITE_OUT_OF_RANGE |
| -- |
| 2.34.1 |
| |
