| From f15ad8025a14a3f11aed0c3d029b9ff39762f88d Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 7 Jan 2022 17:13:49 +0800 |
| Subject: usb: gadget: tegra-xudc: Fix control endpoint's definitions |
| |
| From: Wayne Chang <waynec@nvidia.com> |
| |
| [ Upstream commit 7bd42fb95eb4f98495ccadf467ad15124208ec49 ] |
| |
| According to the Tegra Technical Reference Manual, the seq_num |
| field of control endpoint is not [31:24] but [31:27]. Bit 24 |
| is reserved and bit 26 is splitxstate. |
| |
| The change fixes the wrong control endpoint's definitions. |
| |
| Signed-off-by: Wayne Chang <waynec@nvidia.com> |
| Link: https://lore.kernel.org/r/20220107091349.149798-1-waynec@nvidia.com |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/usb/gadget/udc/tegra-xudc.c | 12 ++++++++++-- |
| 1 file changed, 10 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c |
| index 716d9ab2d2ff..be76f891b9c5 100644 |
| --- a/drivers/usb/gadget/udc/tegra-xudc.c |
| +++ b/drivers/usb/gadget/udc/tegra-xudc.c |
| @@ -272,8 +272,10 @@ BUILD_EP_CONTEXT_RW(deq_hi, deq_hi, 0, 0xffffffff) |
| BUILD_EP_CONTEXT_RW(avg_trb_len, tx_info, 0, 0xffff) |
| BUILD_EP_CONTEXT_RW(max_esit_payload, tx_info, 16, 0xffff) |
| BUILD_EP_CONTEXT_RW(edtla, rsvd[0], 0, 0xffffff) |
| -BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 24, 0xff) |
| +BUILD_EP_CONTEXT_RW(rsvd, rsvd[0], 24, 0x1) |
| BUILD_EP_CONTEXT_RW(partial_td, rsvd[0], 25, 0x1) |
| +BUILD_EP_CONTEXT_RW(splitxstate, rsvd[0], 26, 0x1) |
| +BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 27, 0x1f) |
| BUILD_EP_CONTEXT_RW(cerrcnt, rsvd[1], 18, 0x3) |
| BUILD_EP_CONTEXT_RW(data_offset, rsvd[2], 0, 0x1ffff) |
| BUILD_EP_CONTEXT_RW(numtrbs, rsvd[2], 22, 0x1f) |
| @@ -1554,6 +1556,9 @@ static int __tegra_xudc_ep_set_halt(struct tegra_xudc_ep *ep, bool halt) |
| ep_reload(xudc, ep->index); |
| |
| ep_ctx_write_state(ep->context, EP_STATE_RUNNING); |
| + ep_ctx_write_rsvd(ep->context, 0); |
| + ep_ctx_write_partial_td(ep->context, 0); |
| + ep_ctx_write_splitxstate(ep->context, 0); |
| ep_ctx_write_seq_num(ep->context, 0); |
| |
| ep_reload(xudc, ep->index); |
| @@ -2809,7 +2814,10 @@ static void tegra_xudc_reset(struct tegra_xudc *xudc) |
| xudc->setup_seq_num = 0; |
| xudc->queued_setup_packet = false; |
| |
| - ep_ctx_write_seq_num(ep0->context, xudc->setup_seq_num); |
| + ep_ctx_write_rsvd(ep0->context, 0); |
| + ep_ctx_write_partial_td(ep0->context, 0); |
| + ep_ctx_write_splitxstate(ep0->context, 0); |
| + ep_ctx_write_seq_num(ep0->context, 0); |
| |
| deq_ptr = trb_virt_to_phys(ep0, &ep0->transfer_ring[ep0->deq_ptr]); |
| |
| -- |
| 2.35.1 |
| |
