| From 91d248c3b903b46a58cbc7e8d38d684d3e4007c2 Mon Sep 17 00:00:00 2001 |
| From: Arnaldo Carvalho de Melo <acme@redhat.com> |
| Date: Thu, 1 Jul 2021 13:32:18 -0300 |
| Subject: tools arch x86: Sync the msr-index.h copy with the kernel sources |
| |
| From: Arnaldo Carvalho de Melo <acme@redhat.com> |
| |
| commit 91d248c3b903b46a58cbc7e8d38d684d3e4007c2 upstream. |
| |
| To pick up the changes from these csets: |
| |
| 4ad3278df6fe2b08 ("x86/speculation: Disable RRSBA behavior") |
| d7caac991feeef1b ("x86/cpu/amd: Add Spectral Chicken") |
| |
| That cause no changes to tooling: |
| |
| $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before |
| $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h |
| $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after |
| $ diff -u before after |
| $ |
| |
| Just silences this perf build warning: |
| |
| Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h' |
| diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h |
| |
| Cc: Adrian Hunter <adrian.hunter@intel.com> |
| Cc: Borislav Petkov <bp@suse.de> |
| Cc: Ian Rogers <irogers@google.com> |
| Cc: Jiri Olsa <jolsa@kernel.org> |
| Cc: Namhyung Kim <namhyung@kernel.org> |
| Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> |
| Cc: Peter Zijlstra <peterz@infradead.org> |
| Link: https://lore.kernel.org/lkml/YtQTm9wsB3hxQWvy@kernel.org |
| Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| tools/arch/x86/include/asm/msr-index.h | 4 ++++ |
| 1 file changed, 4 insertions(+) |
| |
| --- a/tools/arch/x86/include/asm/msr-index.h |
| +++ b/tools/arch/x86/include/asm/msr-index.h |
| @@ -93,6 +93,7 @@ |
| #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a |
| #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ |
| #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ |
| +#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ |
| #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ |
| #define ARCH_CAP_SSB_NO BIT(4) /* |
| * Not susceptible to Speculative Store Bypass |
| @@ -561,6 +562,9 @@ |
| /* Fam 17h MSRs */ |
| #define MSR_F17H_IRPERF 0xc00000e9 |
| |
| +#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 |
| +#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) |
| + |
| /* Fam 16h MSRs */ |
| #define MSR_F16H_L2I_PERF_CTL 0xc0010230 |
| #define MSR_F16H_L2I_PERF_CTR 0xc0010231 |
