| From 5e4bfa8008a62e727163476e7b922d90738a0211 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Mon, 7 Oct 2024 13:18:50 +0100 |
| Subject: arm64: errata: Expand speculative SSBS workaround once more |
| |
| From: Mark Rutland <mark.rutland@arm.com> |
| |
| [ Upstream commit 081eb7932c2b244f63317a982c5e3990e2c7fbdd ] |
| |
| A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS |
| special-purpose register does not affect subsequent speculative |
| instructions, permitting speculative store bypassing for a window of |
| time. |
| |
| We worked around this for a number of CPUs in commits: |
| |
| * 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") |
| * 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") |
| * 145502cac7ea70b5 ("arm64: errata: Expand speculative SSBS workaround (again)") |
| |
| Since then, a (hopefully final) batch of updates have been published, |
| with two more affected CPUs. For the affected CPUs the existing |
| mitigation is sufficient, as described in their respective Software |
| Developer Errata Notice (SDEN) documents: |
| |
| * Cortex-A715 (MP148) SDEN v15.0, erratum 3456084 |
| https://developer.arm.com/documentation/SDEN-2148827/1500/ |
| |
| * Neoverse-N3 (MP195) SDEN v5.0, erratum 3456111 |
| https://developer.arm.com/documentation/SDEN-3050973/0500/ |
| |
| Enable the existing mitigation by adding the relevant MIDRs to |
| erratum_spec_ssbs_list, and update silicon-errata.rst and the |
| Kconfig text accordingly. |
| |
| Signed-off-by: Mark Rutland <mark.rutland@arm.com> |
| Cc: James Morse <james.morse@arm.com> |
| Cc: Will Deacon <will@kernel.org> |
| Link: https://lore.kernel.org/r/20240930111705.3352047-3-mark.rutland@arm.com |
| Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
| [ Mark: fix conflict in silicon-errata.rst, handle move ] |
| Signed-off-by: Mark Rutland <mark.rutland@arm.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| Documentation/arm64/silicon-errata.rst | 4 ++++ |
| arch/arm64/Kconfig | 2 ++ |
| arch/arm64/kernel/cpu_errata.c | 2 ++ |
| 3 files changed, 8 insertions(+) |
| |
| diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst |
| index 00755541a9c50..17da972099760 100644 |
| --- a/Documentation/arm64/silicon-errata.rst |
| +++ b/Documentation/arm64/silicon-errata.rst |
| @@ -98,6 +98,8 @@ stable kernels. |
| +----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | |
| +----------------+-----------------+-----------------+-----------------------------+ |
| +| ARM | Cortex-A715 | #3456084 | ARM64_ERRATUM_3194386 | |
| ++----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | |
| +----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | |
| @@ -124,6 +126,8 @@ stable kernels. |
| +----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | |
| +----------------+-----------------+-----------------+-----------------------------+ |
| +| ARM | Neoverse-N3 | #3456111 | ARM64_ERRATUM_3194386 | |
| ++----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | |
| +----------------+-----------------+-----------------+-----------------------------+ |
| | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | |
| diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig |
| index 562558e0915cb..82eba7ffa1d58 100644 |
| --- a/arch/arm64/Kconfig |
| +++ b/arch/arm64/Kconfig |
| @@ -602,6 +602,7 @@ config ARM64_ERRATUM_3194386 |
| * ARM Cortex-A78C erratum 3324346 |
| * ARM Cortex-A78C erratum 3324347 |
| * ARM Cortex-A710 erratam 3324338 |
| + * ARM Cortex-A715 errartum 3456084 |
| * ARM Cortex-A720 erratum 3456091 |
| * ARM Cortex-A725 erratum 3456106 |
| * ARM Cortex-X1 erratum 3324344 |
| @@ -612,6 +613,7 @@ config ARM64_ERRATUM_3194386 |
| * ARM Cortex-X925 erratum 3324334 |
| * ARM Neoverse-N1 erratum 3324349 |
| * ARM Neoverse N2 erratum 3324339 |
| + * ARM Neoverse-N3 erratum 3456111 |
| * ARM Neoverse-V1 erratum 3324341 |
| * ARM Neoverse V2 erratum 3324336 |
| * ARM Neoverse-V3 erratum 3312417 |
| diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c |
| index 20c8d39b71cd6..1e1dfe59a469e 100644 |
| --- a/arch/arm64/kernel/cpu_errata.c |
| +++ b/arch/arm64/kernel/cpu_errata.c |
| @@ -848,6 +848,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = { |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), |
| + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), |
| @@ -858,6 +859,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = { |
| MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), |
| MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), |
| MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), |
| + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), |
| MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), |
| MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), |
| MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), |
| -- |
| 2.43.0 |
| |
