| From foo@baz Sat Dec 19 11:44:48 AM CET 2020 |
| From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Date: Sat, 5 Dec 2020 22:32:07 +0100 |
| Subject: net: stmmac: dwmac-meson8b: fix mask definition of the m250_sel mux |
| |
| From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| |
| [ Upstream commit 82ca4c922b8992013a238d65cf4e60cc33e12f36 ] |
| |
| The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by |
| shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in |
| struct clk_mux expects the mask relative to the "shift" field in the |
| same struct. |
| |
| While here, get rid of the PRG_ETH0_CLK_M250_SEL_SHIFT macro and use |
| __ffs() to determine it from the existing PRG_ETH0_CLK_M250_SEL_MASK |
| macro. |
| |
| Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") |
| Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> |
| Link: https://lore.kernel.org/r/20201205213207.519341-1-martin.blumenstingl@googlemail.com |
| Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 6 +++--- |
| 1 file changed, 3 insertions(+), 3 deletions(-) |
| |
| --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c |
| +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c |
| @@ -29,7 +29,6 @@ |
| #define PRG_ETH0_EXT_RMII_MODE 4 |
| |
| /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ |
| -#define PRG_ETH0_CLK_M250_SEL_SHIFT 4 |
| #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) |
| |
| #define PRG_ETH0_TXDLY_SHIFT 5 |
| @@ -143,8 +142,9 @@ static int meson8b_init_rgmii_tx_clk(str |
| } |
| |
| clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0; |
| - clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; |
| - clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; |
| + clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK); |
| + clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >> |
| + clk_configs->m250_mux.shift; |
| clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names, |
| MUX_CLK_NUM_PARENTS, &clk_mux_ops, |
| &clk_configs->m250_mux.hw); |
