| From a500f3bd787f8224341e44b238f318c407b10897 Mon Sep 17 00:00:00 2001 |
| From: Eugen Hristev <eugen.hristev@microchip.com> |
| Date: Tue, 28 Jan 2020 12:57:39 +0000 |
| Subject: iio: adc: at91-sama5d2_adc: fix differential channels in triggered mode |
| |
| From: Eugen Hristev <eugen.hristev@microchip.com> |
| |
| commit a500f3bd787f8224341e44b238f318c407b10897 upstream. |
| |
| The differential channels require writing the channel offset register (COR). |
| Otherwise they do not work in differential mode. |
| The configuration of COR is missing in triggered mode. |
| |
| Fixes: 5e1a1da0f8c9 ("iio: adc: at91-sama5d2_adc: add hw trigger and buffer support") |
| Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
| Cc: <Stable@vger.kernel.org> |
| Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/iio/adc/at91-sama5d2_adc.c | 15 +++++++++++++++ |
| 1 file changed, 15 insertions(+) |
| |
| --- a/drivers/iio/adc/at91-sama5d2_adc.c |
| +++ b/drivers/iio/adc/at91-sama5d2_adc.c |
| @@ -723,6 +723,7 @@ static int at91_adc_configure_trigger(st |
| |
| for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) { |
| struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit); |
| + u32 cor; |
| |
| if (!chan) |
| continue; |
| @@ -732,6 +733,20 @@ static int at91_adc_configure_trigger(st |
| continue; |
| |
| if (state) { |
| + cor = at91_adc_readl(st, AT91_SAMA5D2_COR); |
| + |
| + if (chan->differential) |
| + cor |= (BIT(chan->channel) | |
| + BIT(chan->channel2)) << |
| + AT91_SAMA5D2_COR_DIFF_OFFSET; |
| + else |
| + cor &= ~(BIT(chan->channel) << |
| + AT91_SAMA5D2_COR_DIFF_OFFSET); |
| + |
| + at91_adc_writel(st, AT91_SAMA5D2_COR, cor); |
| + } |
| + |
| + if (state) { |
| at91_adc_writel(st, AT91_SAMA5D2_CHER, |
| BIT(chan->channel)); |
| /* enable irq only if not using DMA */ |
