| From 5329aaa3189956b271142095681cd8661cb03de8 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 23 Apr 2025 09:12:09 +0200 |
| Subject: net: stmmac: fix dwmac1000 ptp timestamp status offset |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Alexis Lothore <alexis.lothore@bootlin.com> |
| |
| [ Upstream commit 73fa4597bdc035437fbcd84d6be32bd39f1f2149 ] |
| |
| When a PTP interrupt occurs, the driver accesses the wrong offset to |
| learn about the number of available snapshots in the FIFO for dwmac1000: |
| it should be accessing bits 29..25, while it is currently reading bits |
| 19..16 (those are bits about the auxiliary triggers which have generated |
| the timestamps). As a consequence, it does not compute correctly the |
| number of available snapshots, and so possibly do not generate the |
| corresponding clock events if the bogus value ends up being 0. |
| |
| Fix clock events generation by reading the correct bits in the timestamp |
| register for dwmac1000. |
| |
| Fixes: 477c3e1f6363 ("net: stmmac: Introduce dwmac1000 timestamping operations") |
| Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com> |
| Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> |
| Link: https://patch.msgid.link/20250423-stmmac_ts-v2-1-e2cf2bbd61b1@bootlin.com |
| Signed-off-by: Paolo Abeni <pabeni@redhat.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h |
| index 600fea8f712fd..2d5bf1de5d2e4 100644 |
| --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h |
| +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h |
| @@ -331,8 +331,8 @@ enum rtc_control { |
| |
| /* PTP and timestamping registers */ |
| |
| -#define GMAC3_X_ATSNS GENMASK(19, 16) |
| -#define GMAC3_X_ATSNS_SHIFT 16 |
| +#define GMAC3_X_ATSNS GENMASK(29, 25) |
| +#define GMAC3_X_ATSNS_SHIFT 25 |
| |
| #define GMAC_PTP_TCR_ATSFC BIT(24) |
| #define GMAC_PTP_TCR_ATSEN0 BIT(25) |
| -- |
| 2.39.5 |
| |
