| From 9be601135ba8ac69880c01606c82140f2dde105e Mon Sep 17 00:00:00 2001 |
| From: Alvin Lee <alvin.lee2@amd.com> |
| Date: Tue, 7 Nov 2023 17:01:49 -0500 |
| Subject: drm/amd/display: Use DRAM speed from validation for dummy p-state |
| |
| From: Alvin Lee <alvin.lee2@amd.com> |
| |
| commit 9be601135ba8ac69880c01606c82140f2dde105e upstream. |
| |
| [Description] |
| When choosing which dummy p-state latency to use, we |
| need to use the DRAM speed from validation. The DRAMSpeed |
| DML variable can change because we use different input |
| params to DML when populating watermarks set B. |
| |
| Cc: stable@vger.kernel.org # 6.1+ |
| Reviewed-by: Samson Tam <samson.tam@amd.com> |
| Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> |
| Signed-off-by: Alvin Lee <alvin.lee2@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 3 ++- |
| 1 file changed, 2 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c |
| +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c |
| @@ -1964,6 +1964,7 @@ void dcn32_calculate_wm_and_dlg_fpu(stru |
| int i, pipe_idx, vlevel_temp = 0; |
| double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; |
| double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; |
| + double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed; |
| double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; |
| bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != |
| dm_dram_clock_change_unsupported; |
| @@ -2151,7 +2152,7 @@ void dcn32_calculate_wm_and_dlg_fpu(stru |
| } |
| |
| if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { |
| - min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; |
| + min_dram_speed_mts = dram_speed_from_validation; |
| min_dram_speed_mts_margin = 160; |
| |
| context->bw_ctx.dml.soc.dram_clock_change_latency_us = |
