| From 479c5ae2f8a55509b691494cd13691d3dc31d102 Mon Sep 17 00:00:00 2001 |
| From: Marc Zyngier <marc.zyngier@arm.com> |
| Date: Fri, 21 Jun 2013 13:08:47 +0100 |
| Subject: ARM: KVM: add missing dsb before invalidating Stage-2 TLBs |
| |
| From: Marc Zyngier <marc.zyngier@arm.com> |
| |
| commit 479c5ae2f8a55509b691494cd13691d3dc31d102 upstream. |
| |
| When performing a Stage-2 TLB invalidation, it is necessary to |
| make sure the write to the page tables is observable by all CPUs. |
| |
| For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa |
| before doing the TLB invalidation itself. |
| |
| Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
| Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> |
| Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/kvm/interrupts.S | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| --- a/arch/arm/kvm/interrupts.S |
| +++ b/arch/arm/kvm/interrupts.S |
| @@ -49,6 +49,7 @@ __kvm_hyp_code_start: |
| ENTRY(__kvm_tlb_flush_vmid_ipa) |
| push {r2, r3} |
| |
| + dsb ishst |
| add r0, r0, #KVM_VTTBR |
| ldrd r2, r3, [r0] |
| mcrr p15, 6, r2, r3, c2 @ Write VTTBR |
