| From c44e60a5e2304c0ff17d925760fab2e12f69a2a6 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 14 May 2020 19:02:37 +0200 |
| Subject: ARM: dts/imx6q-bx50v3: Set display interface clock parents |
| |
| From: Robert Beckett <bob.beckett@collabora.com> |
| |
| [ Upstream commit 665e7c73a7724a393b4ec92d1ae1e029925ef2b7 ] |
| |
| Avoid LDB and IPU DI clocks both using the same parent. LDB requires |
| pasthrough clock to avoid breaking timing while IPU DI does not. |
| |
| Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent |
| and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV. |
| |
| This fixes an issue where attempting atomic modeset while using |
| HDMI and display port at the same time causes LDB clock programming |
| to destroy the programming of HDMI that was done during the same |
| modeset. |
| |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Robert Beckett <bob.beckett@collabora.com> |
| [Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M |
| originally chosen by Robert Beckett to avoid affecting eMMC clock |
| by DRM atomic updates] |
| Signed-off-by: Ian Ray <ian.ray@ge.com> |
| [Squash Robert's and Ian's commits for bisectability, update patch |
| description and add stable tag] |
| Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> |
| Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm/boot/dts/imx6q-b450v3.dts | 7 ------- |
| arch/arm/boot/dts/imx6q-b650v3.dts | 7 ------- |
| arch/arm/boot/dts/imx6q-b850v3.dts | 11 ----------- |
| arch/arm/boot/dts/imx6q-bx50v3.dtsi | 15 +++++++++++++++ |
| 4 files changed, 15 insertions(+), 25 deletions(-) |
| |
| diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts |
| index 404a93d9596b..dc7d65da7d01 100644 |
| --- a/arch/arm/boot/dts/imx6q-b450v3.dts |
| +++ b/arch/arm/boot/dts/imx6q-b450v3.dts |
| @@ -65,13 +65,6 @@ |
| }; |
| }; |
| |
| -&clks { |
| - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; |
| - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, |
| - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
| -}; |
| - |
| &ldb { |
| status = "okay"; |
| |
| diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts |
| index 7f9f176901d4..101d61f93070 100644 |
| --- a/arch/arm/boot/dts/imx6q-b650v3.dts |
| +++ b/arch/arm/boot/dts/imx6q-b650v3.dts |
| @@ -65,13 +65,6 @@ |
| }; |
| }; |
| |
| -&clks { |
| - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; |
| - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, |
| - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
| -}; |
| - |
| &ldb { |
| status = "okay"; |
| |
| diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts |
| index 46bdc6722715..8fc831dc3156 100644 |
| --- a/arch/arm/boot/dts/imx6q-b850v3.dts |
| +++ b/arch/arm/boot/dts/imx6q-b850v3.dts |
| @@ -53,17 +53,6 @@ |
| }; |
| }; |
| |
| -&clks { |
| - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| - <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
| - <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, |
| - <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; |
| - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, |
| - <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, |
| - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, |
| - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; |
| -}; |
| - |
| &ldb { |
| fsl,dual-channel; |
| status = "okay"; |
| diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi |
| index 8420378d095d..f3c2c5587616 100644 |
| --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi |
| +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi |
| @@ -388,3 +388,18 @@ |
| #interrupt-cells = <1>; |
| }; |
| }; |
| + |
| +&clks { |
| + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
| + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, |
| + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>, |
| + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>, |
| + <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>; |
| + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, |
| + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, |
| + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, |
| + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, |
| + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, |
| + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; |
| +}; |
| -- |
| 2.25.1 |
| |