| From foo@baz Sat Mar 19 01:51:18 PM CET 2022 |
| From: James Morse <james.morse@arm.com> |
| Date: Fri, 18 Mar 2022 17:48:21 +0000 |
| Subject: arm64: Add part number for Arm Cortex-A77 |
| To: stable@vger.kernel.org |
| Cc: linux-kernel@vger.kernel.org, james.morse@arm.com, catalin.marinas@arm.com |
| Message-ID: <20220318174842.2321061-2-james.morse@arm.com> |
| |
| From: Rob Herring <robh@kernel.org> |
| |
| commit 8a6b88e66233f5f1779b0a1342aa9dc030dddcd5 upstream. |
| |
| Add the MIDR part number info for the Arm Cortex-A77. |
| |
| Signed-off-by: Rob Herring <robh@kernel.org> |
| Acked-by: Catalin Marinas <catalin.marinas@arm.com> |
| Cc: Catalin Marinas <catalin.marinas@arm.com> |
| Cc: Will Deacon <will@kernel.org> |
| Link: https://lore.kernel.org/r/20201028182839.166037-1-robh@kernel.org |
| Signed-off-by: Will Deacon <will@kernel.org> |
| Signed-off-by: James Morse <james.morse@arm.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/arm64/include/asm/cputype.h | 2 ++ |
| 1 file changed, 2 insertions(+) |
| |
| --- a/arch/arm64/include/asm/cputype.h |
| +++ b/arch/arm64/include/asm/cputype.h |
| @@ -81,6 +81,7 @@ |
| #define ARM_CPU_PART_CORTEX_A55 0xD05 |
| #define ARM_CPU_PART_CORTEX_A76 0xD0B |
| #define ARM_CPU_PART_NEOVERSE_N1 0xD0C |
| +#define ARM_CPU_PART_CORTEX_A77 0xD0D |
| |
| #define APM_CPU_PART_POTENZA 0x000 |
| |
| @@ -109,6 +110,7 @@ |
| #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) |
| #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) |
| #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) |
| +#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) |
| #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) |
| #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) |
| #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) |
