blob: c58dcab778c2277bc47ffaf819a4572fd10d30df [file] [log] [blame]
From bff0a764bdc7e8c6705f19722cf1d07dae4b31fc Mon Sep 17 00:00:00 2001
From: Sasha Levin <sashal@kernel.org>
Date: Thu, 16 Aug 2018 10:06:03 +0200
Subject: ARM: dts: tegra20: restore address order
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
[ Upstream commit 8188391c127ea34d66f37eda6755d0acb51dc600 ]
Commit 6c468f109884 ("ARM: dts: tegra: add Tegra20 NAND flash
controller node") introduced the nand-controller node. However, it got
added at the wrong spot not honoring the address order. Fix this.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f04..80854f7de765c 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -419,19 +419,6 @@
status = "disabled";
};
- gmi@70009000 {
- compatible = "nvidia,tegra20-gmi";
- reg = <0x70009000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xd0000000 0xfffffff>;
- clocks = <&tegra_car TEGRA20_CLK_NOR>;
- clock-names = "gmi";
- resets = <&tegra_car 42>;
- reset-names = "gmi";
- status = "disabled";
- };
-
nand-controller@70008000 {
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
@@ -447,6 +434,19 @@
status = "disabled";
};
+ gmi@70009000 {
+ compatible = "nvidia,tegra20-gmi";
+ reg = <0x70009000 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd0000000 0xfffffff>;
+ clocks = <&tegra_car TEGRA20_CLK_NOR>;
+ clock-names = "gmi";
+ resets = <&tegra_car 42>;
+ reset-names = "gmi";
+ status = "disabled";
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.20.1