| From 646d79986d2497ad233607269fde1e75acc24351 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 20 Sep 2018 13:18:02 -0600 |
| Subject: coresight: tmc: Fix byte-address alignment for RRP |
| |
| From: Leo Yan <leo.yan@linaro.org> |
| |
| [ Upstream commit e7753f3937610633a540f2be81be87531f96ff04 ] |
| |
| >From the comment in the code, it claims the requirement for byte-address |
| alignment for RRP register: 'for 32-bit, 64-bit and 128-bit wide trace |
| memory, the four LSBs must be 0s. For 256-bit wide trace memory, the |
| five LSBs must be 0s'. This isn't consistent with the program, the |
| program sets five LSBs as zeros for 32/64/128-bit wide trace memory and |
| set six LSBs zeros for 256-bit wide trace memory. |
| |
| After checking with the CoreSight Trace Memory Controller technical |
| reference manual (ARM DDI 0461B, section 3.3.4 RAM Read Pointer |
| Register), it proves the comment is right and the program does wrong |
| setting. |
| |
| This patch fixes byte-address alignment for RRP by following correct |
| definition in the technical reference manual. |
| |
| Cc: Mathieu Poirier <mathieu.poirier@linaro.org> |
| Cc: Mike Leach <mike.leach@linaro.org> |
| Signed-off-by: Leo Yan <leo.yan@linaro.org> |
| Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c |
| index 0549249f4b398..e31061308e19e 100644 |
| --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c |
| +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c |
| @@ -438,10 +438,10 @@ static void tmc_update_etf_buffer(struct coresight_device *csdev, |
| case TMC_MEM_INTF_WIDTH_32BITS: |
| case TMC_MEM_INTF_WIDTH_64BITS: |
| case TMC_MEM_INTF_WIDTH_128BITS: |
| - mask = GENMASK(31, 5); |
| + mask = GENMASK(31, 4); |
| break; |
| case TMC_MEM_INTF_WIDTH_256BITS: |
| - mask = GENMASK(31, 6); |
| + mask = GENMASK(31, 5); |
| break; |
| } |
| |
| -- |
| 2.20.1 |
| |