| From foo@baz Sun May 27 17:33:38 CEST 2018 |
| From: Marc Zyngier <marc.zyngier@arm.com> |
| Date: Fri, 9 Mar 2018 15:40:50 +0000 |
| Subject: arm64: Relax ARM_SMCCC_ARCH_WORKAROUND_1 discovery |
| |
| From: Marc Zyngier <marc.zyngier@arm.com> |
| |
| [ Upstream commit e21da1c992007594d391e7b301779cf30f438691 ] |
| |
| A recent update to the ARM SMCCC ARCH_WORKAROUND_1 specification |
| allows firmware to return a non zero, positive value to describe |
| that although the mitigation is implemented at the higher exception |
| level, the CPU on which the call is made is not affected. |
| |
| Let's relax the check on the return value from ARCH_WORKAROUND_1 |
| so that we only error out if the returned value is negative. |
| |
| Fixes: b092201e0020 ("arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support") |
| Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
| Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/arm64/kernel/cpu_errata.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/arch/arm64/kernel/cpu_errata.c |
| +++ b/arch/arm64/kernel/cpu_errata.c |
| @@ -160,7 +160,7 @@ static int enable_smccc_arch_workaround_ |
| case PSCI_CONDUIT_HVC: |
| arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, |
| ARM_SMCCC_ARCH_WORKAROUND_1, &res); |
| - if (res.a0) |
| + if ((int)res.a0 < 0) |
| return 0; |
| cb = call_hvc_arch_workaround_1; |
| smccc_start = __smccc_workaround_1_hvc_start; |
| @@ -170,7 +170,7 @@ static int enable_smccc_arch_workaround_ |
| case PSCI_CONDUIT_SMC: |
| arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, |
| ARM_SMCCC_ARCH_WORKAROUND_1, &res); |
| - if (res.a0) |
| + if ((int)res.a0 < 0) |
| return 0; |
| cb = call_smc_arch_workaround_1; |
| smccc_start = __smccc_workaround_1_smc_start; |
