| From 40db569d6769ffa3864fd1b89616b1a7323568a8 Mon Sep 17 00:00:00 2001 |
| From: Dmitry Osipenko <digetx@gmail.com> |
| Date: Fri, 12 Apr 2019 00:48:34 +0300 |
| Subject: clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider |
| |
| From: Dmitry Osipenko <digetx@gmail.com> |
| |
| commit 40db569d6769ffa3864fd1b89616b1a7323568a8 upstream. |
| |
| There are wrongly set parenthesis in the code that are resulting in a |
| wrong configuration being programmed for PLLM. The original fix was made |
| by Danny Huang in the downstream kernel. The patch was tested on Nyan Big |
| Tegra124 chromebook, PLLM rate changing works correctly now and system |
| doesn't lock up after changing the PLLM rate due to EMC scaling. |
| |
| Cc: <stable@vger.kernel.org> |
| Tested-by: Steev Klimaszewski <steev@kali.org> |
| Signed-off-by: Dmitry Osipenko <digetx@gmail.com> |
| Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/tegra/clk-pll.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/clk/tegra/clk-pll.c |
| +++ b/drivers/clk/tegra/clk-pll.c |
| @@ -638,8 +638,8 @@ static void _update_pll_mnp(struct tegra |
| pll_override_writel(val, params->pmc_divp_reg, pll); |
| |
| val = pll_override_readl(params->pmc_divnm_reg, pll); |
| - val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | |
| - ~(divn_mask(pll) << div_nmp->override_divn_shift); |
| + val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | |
| + (divn_mask(pll) << div_nmp->override_divn_shift)); |
| val |= (cfg->m << div_nmp->override_divm_shift) | |
| (cfg->n << div_nmp->override_divn_shift); |
| pll_override_writel(val, params->pmc_divnm_reg, pll); |