| From 86fa6a344209d9414ea962b1f1ac6ade9dd7563a Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Stefan=20M=C3=A4tje?= <stefan.maetje@esd.eu> |
| Date: Fri, 29 Mar 2019 18:07:34 +0100 |
| Subject: PCI: Factor out pcie_retrain_link() function |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Stefan Mätje <stefan.maetje@esd.eu> |
| |
| commit 86fa6a344209d9414ea962b1f1ac6ade9dd7563a upstream. |
| |
| Factor out pcie_retrain_link() to use for Pericom Retrain Link quirk. No |
| functional change intended. |
| |
| Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu> |
| Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
| Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
| CC: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++---------------- |
| 1 file changed, 24 insertions(+), 16 deletions(-) |
| |
| --- a/drivers/pci/pcie/aspm.c |
| +++ b/drivers/pci/pcie/aspm.c |
| @@ -172,6 +172,29 @@ static void pcie_clkpm_cap_init(struct p |
| link->clkpm_capable = (blacklist) ? 0 : capable; |
| } |
| |
| +static bool pcie_retrain_link(struct pcie_link_state *link) |
| +{ |
| + struct pci_dev *parent = link->pdev; |
| + unsigned long start_jiffies; |
| + u16 reg16; |
| + |
| + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); |
| + reg16 |= PCI_EXP_LNKCTL_RL; |
| + pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
| + |
| + /* Wait for link training end. Break out after waiting for timeout */ |
| + start_jiffies = jiffies; |
| + for (;;) { |
| + pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
| + if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
| + break; |
| + if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
| + break; |
| + msleep(1); |
| + } |
| + return !(reg16 & PCI_EXP_LNKSTA_LT); |
| +} |
| + |
| /* |
| * pcie_aspm_configure_common_clock: check if the 2 ends of a link |
| * could use common clock. If they are, configure them to use the |
| @@ -181,7 +204,6 @@ static void pcie_aspm_configure_common_c |
| { |
| int same_clock = 1; |
| u16 reg16, parent_reg, child_reg[8]; |
| - unsigned long start_jiffies; |
| struct pci_dev *child, *parent = link->pdev; |
| struct pci_bus *linkbus = parent->subordinate; |
| /* |
| @@ -221,21 +243,7 @@ static void pcie_aspm_configure_common_c |
| reg16 &= ~PCI_EXP_LNKCTL_CCC; |
| pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
| |
| - /* Retrain link */ |
| - reg16 |= PCI_EXP_LNKCTL_RL; |
| - pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
| - |
| - /* Wait for link training end. Break out after waiting for timeout */ |
| - start_jiffies = jiffies; |
| - for (;;) { |
| - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
| - if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
| - break; |
| - if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
| - break; |
| - msleep(1); |
| - } |
| - if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
| + if (pcie_retrain_link(link)) |
| return; |
| |
| /* Training failed. Restore common clock configurations */ |