| From 9401d5aa328e64617d87abd59af1c91cace4c3e4 Mon Sep 17 00:00:00 2001 |
| From: Paul Cercueil <paul@crapouillou.net> |
| Date: Fri, 6 Mar 2020 23:29:27 +0100 |
| Subject: ASoC: jz4740-i2s: Fix divider written at incorrect offset in register |
| |
| From: Paul Cercueil <paul@crapouillou.net> |
| |
| commit 9401d5aa328e64617d87abd59af1c91cace4c3e4 upstream. |
| |
| The 4-bit divider value was written at offset 8, while the jz4740 |
| programming manual locates it at offset 0. |
| |
| Fixes: 26b0aad80a86 ("ASoC: jz4740: Add dynamic sampling rate support to jz4740-i2s") |
| Signed-off-by: Paul Cercueil <paul@crapouillou.net> |
| Cc: stable@vger.kernel.org |
| Link: https://lore.kernel.org/r/20200306222931.39664-2-paul@crapouillou.net |
| Signed-off-by: Mark Brown <broonie@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| sound/soc/jz4740/jz4740-i2s.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/sound/soc/jz4740/jz4740-i2s.c |
| +++ b/sound/soc/jz4740/jz4740-i2s.c |
| @@ -92,7 +92,7 @@ |
| #define JZ_AIC_I2S_STATUS_BUSY BIT(2) |
| |
| #define JZ_AIC_CLK_DIV_MASK 0xf |
| -#define I2SDIV_DV_SHIFT 8 |
| +#define I2SDIV_DV_SHIFT 0 |
| #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) |
| #define I2SDIV_IDV_SHIFT 8 |
| #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) |
