| From 3b24b62cb811ba5e5bc07039417bcd849965de23 Mon Sep 17 00:00:00 2001 |
| From: Michael Tretter <m.tretter@pengutronix.de> |
| Date: Tue, 19 Mar 2019 11:01:46 +0100 |
| Subject: clk: zynqmp: fix check for fractional clock |
| |
| [ Upstream commit c06e64407e031e71c67f45f07981510ca4c880a1 ] |
| |
| The firmware sets BIT(13) in clkflag to mark a divider as fractional |
| divider. The clock driver copies the clkflag straight to the flags of |
| the common clock framework. In the common clk framework flags, BIT(13) |
| is defined as CLK_DUTY_CYCLE_PARENT. |
| |
| Add a new field to the zynqmp_clk_divider to specify if a divider is a |
| fractional devider. Set this field based on the clkflag when registering |
| a divider. |
| |
| At the same time, unset BIT(13) from clkflag when copying the flags to |
| the common clk framework flags. |
| |
| Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/zynqmp/divider.c | 9 ++++++--- |
| 1 file changed, 6 insertions(+), 3 deletions(-) |
| |
| diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c |
| index a371c66e72ef6..bd9b5fbc443b3 100644 |
| --- a/drivers/clk/zynqmp/divider.c |
| +++ b/drivers/clk/zynqmp/divider.c |
| @@ -31,12 +31,14 @@ |
| * struct zynqmp_clk_divider - adjustable divider clock |
| * @hw: handle between common and hardware-specific interfaces |
| * @flags: Hardware specific flags |
| + * @is_frac: The divider is a fractional divider |
| * @clk_id: Id of clock |
| * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) |
| */ |
| struct zynqmp_clk_divider { |
| struct clk_hw hw; |
| u8 flags; |
| + bool is_frac; |
| u32 clk_id; |
| u32 div_type; |
| }; |
| @@ -116,8 +118,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, |
| |
| bestdiv = zynqmp_divider_get_val(*prate, rate); |
| |
| - if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && |
| - (divider->flags & CLK_FRAC)) |
| + if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) |
| bestdiv = rate % *prate ? 1 : bestdiv; |
| *prate = rate * bestdiv; |
| |
| @@ -195,11 +196,13 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, |
| |
| init.name = name; |
| init.ops = &zynqmp_clk_divider_ops; |
| - init.flags = nodes->flag; |
| + /* CLK_FRAC is not defined in the common clk framework */ |
| + init.flags = nodes->flag & ~CLK_FRAC; |
| init.parent_names = parents; |
| init.num_parents = 1; |
| |
| /* struct clk_divider assignments */ |
| + div->is_frac = !!(nodes->flag & CLK_FRAC); |
| div->flags = nodes->type_flag; |
| div->hw.init = &init; |
| div->clk_id = clk_id; |
| -- |
| 2.20.1 |
| |