| From 09f91381fa5de1d44bc323d8bf345f5d57b3d9b5 Mon Sep 17 00:00:00 2001 |
| From: Peter Geis <pgwipeout@gmail.com> |
| Date: Wed, 13 Mar 2019 19:02:30 +0000 |
| Subject: arm64: dts: rockchip: fix rk3328 sdmmc0 write errors |
| |
| From: Peter Geis <pgwipeout@gmail.com> |
| |
| commit 09f91381fa5de1d44bc323d8bf345f5d57b3d9b5 upstream. |
| |
| Various rk3328 based boards experience occasional sdmmc0 write errors. |
| This is due to the rk3328.dtsi tx drive levels being set to 4ma, vs |
| 8ma per the rk3328 datasheet default settings. |
| |
| Fix this by setting the tx signal pins to 8ma. |
| Inspiration from tonymac32's patch, |
| https://github.com/ayufan-rock64/linux-kernel/commit/dc1212b347e0da17c5460bcc0a56b07d02bac3f8 |
| |
| Fixes issues on the rk3328-roc-cc and the rk3328-rock64 (as per the |
| above commit message). |
| |
| Tested on the rk3328-roc-cc board. |
| |
| Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Peter Geis <pgwipeout@gmail.com> |
| Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 +++++++------- |
| 1 file changed, 7 insertions(+), 7 deletions(-) |
| |
| --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi |
| +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi |
| @@ -1431,11 +1431,11 @@ |
| |
| sdmmc0 { |
| sdmmc0_clk: sdmmc0-clk { |
| - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; |
| + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; |
| }; |
| |
| sdmmc0_cmd: sdmmc0-cmd { |
| - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; |
| + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; |
| }; |
| |
| sdmmc0_dectn: sdmmc0-dectn { |
| @@ -1447,14 +1447,14 @@ |
| }; |
| |
| sdmmc0_bus1: sdmmc0-bus1 { |
| - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>; |
| + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; |
| }; |
| |
| sdmmc0_bus4: sdmmc0-bus4 { |
| - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>, |
| - <1 RK_PA1 1 &pcfg_pull_up_4ma>, |
| - <1 RK_PA2 1 &pcfg_pull_up_4ma>, |
| - <1 RK_PA3 1 &pcfg_pull_up_4ma>; |
| + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, |
| + <1 RK_PA1 1 &pcfg_pull_up_8ma>, |
| + <1 RK_PA2 1 &pcfg_pull_up_8ma>, |
| + <1 RK_PA3 1 &pcfg_pull_up_8ma>; |
| }; |
| |
| sdmmc0_gpio: sdmmc0-gpio { |