| From fea7fda7f50a6059220f83251e70709e45cc8040 Mon Sep 17 00:00:00 2001 |
| From: Florian Fainelli <f.fainelli@gmail.com> |
| Date: Thu, 3 Oct 2019 11:43:51 -0700 |
| Subject: net: phy: broadcom: Fix RGMII delays configuration for BCM54210E |
| |
| From: Florian Fainelli <f.fainelli@gmail.com> |
| |
| commit fea7fda7f50a6059220f83251e70709e45cc8040 upstream. |
| |
| Commit 0fc9ae107669 ("net: phy: broadcom: add support for |
| BCM54210E") added support for BCM54210E but also unconditionally cleared |
| the RXC to RXD skew and the TXD to TXC skew, thus only making |
| PHY_INTERFACE_MODE_RGMII a possible configuration. Use |
| bcm54xx_config_clock_delay() which correctly sets the registers |
| depending on the 4 possible PHY interface values that exist for RGMII. |
| |
| Fixes: 0fc9ae107669 ("net: phy: broadcom: add support for BCM54210E") |
| Reported-by: Manasa Mudireddy <manasa.mudireddy@broadcom.com> |
| Reported-by: Ray Jui <ray.jui@broadcom.com> |
| Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/net/phy/broadcom.c | 11 +++-------- |
| 1 file changed, 3 insertions(+), 8 deletions(-) |
| |
| --- a/drivers/net/phy/broadcom.c |
| +++ b/drivers/net/phy/broadcom.c |
| @@ -26,18 +26,13 @@ MODULE_DESCRIPTION("Broadcom PHY driver" |
| MODULE_AUTHOR("Maciej W. Rozycki"); |
| MODULE_LICENSE("GPL"); |
| |
| +static int bcm54xx_config_clock_delay(struct phy_device *phydev); |
| + |
| static int bcm54210e_config_init(struct phy_device *phydev) |
| { |
| int val; |
| |
| - val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); |
| - val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; |
| - val |= MII_BCM54XX_AUXCTL_MISC_WREN; |
| - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val); |
| - |
| - val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); |
| - val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; |
| - bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); |
| + bcm54xx_config_clock_delay(phydev); |
| |
| if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { |
| val = phy_read(phydev, MII_CTRL1000); |
