| From c82bf6e133d30e0f9172a20807814fa28aef0f67 Mon Sep 17 00:00:00 2001 |
| From: Joel Stanley <joel@jms.id.au> |
| Date: Wed, 12 Aug 2020 20:54:00 +0930 |
| Subject: ARM: aspeed: g5: Do not set sirq polarity |
| |
| From: Joel Stanley <joel@jms.id.au> |
| |
| commit c82bf6e133d30e0f9172a20807814fa28aef0f67 upstream. |
| |
| A feature was added to the aspeed vuart driver to configure the vuart |
| interrupt (sirq) polarity according to the LPC/eSPI strapping register. |
| |
| Systems that depend on a active low behaviour (sirq_polarity set to 0) |
| such as OpenPower boxes also use LPC, so this relationship does not |
| hold. Jeremy confirms that the s2600st which is strapped for eSPI also |
| does not have this relationship. |
| |
| The property was added for a Tyan S7106 system which is not supported |
| in the kernel tree. Should this or other systems wish to use this |
| feature of the driver they should add it to the machine specific device |
| tree. |
| |
| Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...") |
| Signed-off-by: Joel Stanley <joel@jms.id.au> |
| Tested-by: Jeremy Kerr <jk@ozlabs.org> |
| Reviewed-by: Jeremy Kerr <jk@ozlabs.org> |
| Cc: stable@vger.kernel.org |
| Link: https://lore.kernel.org/r/20200812112400.2406734-1-joel@jms.id.au |
| Signed-off-by: Joel Stanley <joel@jms.id.au> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/boot/dts/aspeed-g5.dtsi | 1 - |
| 1 file changed, 1 deletion(-) |
| |
| --- a/arch/arm/boot/dts/aspeed-g5.dtsi |
| +++ b/arch/arm/boot/dts/aspeed-g5.dtsi |
| @@ -425,7 +425,6 @@ |
| interrupts = <8>; |
| clocks = <&syscon ASPEED_CLK_APB>; |
| no-loopback-test; |
| - aspeed,sirq-polarity-sense = <&syscon 0x70 25>; |
| status = "disabled"; |
| }; |
| |