| From 60d804521ec4cd01217a96f33cd1bb29e295333d Mon Sep 17 00:00:00 2001 |
| From: Kim Phillips <kim.phillips@amd.com> |
| Date: Tue, 1 Sep 2020 17:09:41 -0500 |
| Subject: perf vendor events amd: Add L2 Prefetch events for zen1 |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
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| |
| From: Kim Phillips <kim.phillips@amd.com> |
| |
| commit 60d804521ec4cd01217a96f33cd1bb29e295333d upstream. |
| |
| Later revisions of PPRs that post-date the original Family 17h events |
| submission patch add these events. |
| |
| Specifically, they were not in this 2017 revision of the F17h PPR: |
| |
| Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors Rev 1.14 - April 15, 2017 |
| |
| But e.g., are included in this 2019 version of the PPR: |
| |
| Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors Rev. 3.14 - Sep 26, 2019 |
| |
| Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family 17h") |
| Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 |
| Signed-off-by: Kim Phillips <kim.phillips@amd.com> |
| Reviewed-by: Ian Rogers <irogers@google.com> |
| Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| Cc: Andi Kleen <ak@linux.intel.com> |
| Cc: Borislav Petkov <bp@suse.de> |
| Cc: Jin Yao <yao.jin@linux.intel.com> |
| Cc: Jiri Olsa <jolsa@redhat.com> |
| Cc: John Garry <john.garry@huawei.com> |
| Cc: Jon Grimm <jon.grimm@amd.com> |
| Cc: Kan Liang <kan.liang@linux.intel.com> |
| Cc: Mark Rutland <mark.rutland@arm.com> |
| Cc: Martin Jambor <mjambor@suse.cz> |
| Cc: Martin Liลกka <mliska@suse.cz> |
| Cc: Michael Petlan <mpetlan@redhat.com> |
| Cc: Namhyung Kim <namhyung@kernel.org> |
| Cc: Peter Zijlstra <peterz@infradead.org> |
| Cc: stable@vger.kernel.org |
| Cc: Stephane Eranian <eranian@google.com> |
| Cc: Vijay Thakkar <vijaythakkar@me.com> |
| Cc: William Cohen <wcohen@redhat.com> |
| Cc: Yunfeng Ye <yeyunfeng@huawei.com> |
| Link: http://lore.kernel.org/lkml/20200901220944.277505-1-kim.phillips@amd.com |
| Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| tools/perf/pmu-events/arch/x86/amdzen1/cache.json | 18 ++++++++++++++++++ |
| 1 file changed, 18 insertions(+) |
| |
| --- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json |
| +++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json |
| @@ -250,6 +250,24 @@ |
| "UMask": "0x1" |
| }, |
| { |
| + "EventName": "l2_pf_hit_l2", |
| + "EventCode": "0x70", |
| + "BriefDescription": "L2 prefetch hit in L2.", |
| + "UMask": "0xff" |
| + }, |
| + { |
| + "EventName": "l2_pf_miss_l2_hit_l3", |
| + "EventCode": "0x71", |
| + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.", |
| + "UMask": "0xff" |
| + }, |
| + { |
| + "EventName": "l2_pf_miss_l2_l3", |
| + "EventCode": "0x72", |
| + "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.", |
| + "UMask": "0xff" |
| + }, |
| + { |
| "EventName": "l3_request_g1.caching_l3_cache_accesses", |
| "EventCode": "0x01", |
| "BriefDescription": "Caching: L3 cache accesses", |