| From 36e1be8ada994d509538b3b1d0af8b63c351e729 Mon Sep 17 00:00:00 2001 |
| From: Kim Phillips <kim.phillips@amd.com> |
| Date: Tue, 8 Sep 2020 16:47:38 -0500 |
| Subject: perf/x86/amd/ibs: Fix raw sample data accumulation |
| |
| From: Kim Phillips <kim.phillips@amd.com> |
| |
| commit 36e1be8ada994d509538b3b1d0af8b63c351e729 upstream. |
| |
| Neither IbsBrTarget nor OPDATA4 are populated in IBS Fetch mode. |
| Don't accumulate them into raw sample user data in that case. |
| |
| Also, in Fetch mode, add saving the IBS Fetch Control Extended MSR. |
| |
| Technically, there is an ABI change here with respect to the IBS raw |
| sample data format, but I don't see any perf driver version information |
| being included in perf.data file headers, but, existing users can detect |
| whether the size of the sample record has reduced by 8 bytes to |
| determine whether the IBS driver has this fix. |
| |
| Fixes: 904cb3677f3a ("perf/x86/amd/ibs: Update IBS MSRs and feature definitions") |
| Reported-by: Stephane Eranian <stephane.eranian@google.com> |
| Signed-off-by: Kim Phillips <kim.phillips@amd.com> |
| Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> |
| Cc: stable@vger.kernel.org |
| Link: https://lkml.kernel.org/r/20200908214740.18097-6-kim.phillips@amd.com |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/x86/events/amd/ibs.c | 26 ++++++++++++++++---------- |
| arch/x86/include/asm/msr-index.h | 1 + |
| 2 files changed, 17 insertions(+), 10 deletions(-) |
| |
| --- a/arch/x86/events/amd/ibs.c |
| +++ b/arch/x86/events/amd/ibs.c |
| @@ -636,18 +636,24 @@ fail: |
| perf_ibs->offset_max, |
| offset + 1); |
| } while (offset < offset_max); |
| + /* |
| + * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately |
| + * depending on their availability. |
| + * Can't add to offset_max as they are staggered |
| + */ |
| if (event->attr.sample_type & PERF_SAMPLE_RAW) { |
| - /* |
| - * Read IbsBrTarget and IbsOpData4 separately |
| - * depending on their availability. |
| - * Can't add to offset_max as they are staggered |
| - */ |
| - if (ibs_caps & IBS_CAPS_BRNTRGT) { |
| - rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++); |
| - size++; |
| + if (perf_ibs == &perf_ibs_op) { |
| + if (ibs_caps & IBS_CAPS_BRNTRGT) { |
| + rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++); |
| + size++; |
| + } |
| + if (ibs_caps & IBS_CAPS_OPDATA4) { |
| + rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++); |
| + size++; |
| + } |
| } |
| - if (ibs_caps & IBS_CAPS_OPDATA4) { |
| - rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++); |
| + if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) { |
| + rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++); |
| size++; |
| } |
| } |
| --- a/arch/x86/include/asm/msr-index.h |
| +++ b/arch/x86/include/asm/msr-index.h |
| @@ -464,6 +464,7 @@ |
| #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) |
| #define MSR_AMD64_IBSCTL 0xc001103a |
| #define MSR_AMD64_IBSBRTARGET 0xc001103b |
| +#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c |
| #define MSR_AMD64_IBSOPDATA4 0xc001103d |
| #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
| #define MSR_AMD64_SEV 0xc0010131 |