| From d183c81929beeba842b74422f754446ef2b8b49c Mon Sep 17 00:00:00 2001 |
| From: Nikita Yushchenko <nyushchenko@dev.rtsoft.ru> |
| Date: Mon, 28 Apr 2014 19:23:44 +0400 |
| Subject: fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6 |
| |
| From: Nikita Yushchenko <nyushchenko@dev.rtsoft.ru> |
| |
| commit d183c81929beeba842b74422f754446ef2b8b49c upstream. |
| |
| Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller |
| present in these SoCs has bit 17 of USBx_CONTROL register marked as |
| Reserved - there is no PHY_CLK_VALID bit there. |
| |
| Testing for this bit in ehci_fsl_setup_phy() behaves differently on two |
| P1020RDB boards available here - on one board test passes and fsl-usb |
| init succeeds, but on other board test fails, causing fsl-usb init to |
| fail. |
| |
| This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on |
| controller version 1.6 that (per manual) does not have this bit. |
| |
| Signed-off-by: Nikita Yushchenko <nyushchenko@dev.rtsoft.ru> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/usb/host/ehci-fsl.c | 3 ++- |
| 1 file changed, 2 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/usb/host/ehci-fsl.c |
| +++ b/drivers/usb/host/ehci-fsl.c |
| @@ -261,7 +261,8 @@ static int ehci_fsl_setup_phy(struct usb |
| break; |
| } |
| |
| - if (pdata->have_sysif_regs && pdata->controller_ver && |
| + if (pdata->have_sysif_regs && |
| + pdata->controller_ver > FSL_USB_VER_1_6 && |
| (phy_mode == FSL_USB2_PHY_ULPI)) { |
| /* check PHY_CLK_VALID to get phy clk valid */ |
| if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) & |
