| From foo@baz Fri Mar 16 15:43:17 CET 2018 |
| From: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Date: Thu, 16 Nov 2017 12:16:00 +0900 |
| Subject: pinctrl: sh-pfc: r8a7795-es1: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D |
| |
| From: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| |
| |
| [ Upstream commit b16cd900de7911f96af17327a081a2141a0b763f ] |
| |
| This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] |
| value when STP_ISEN_1_D pin function is selected for IPSR16 bit[27:24]. |
| |
| This is a correction to the incorrect implementation of MOD_SEL register |
| pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware |
| User's Manual Rev.0.51E. |
| |
| Fixes: 0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support) |
| Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c |
| @@ -1397,7 +1397,7 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), |
| PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), |
| PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), |
| - PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), |
| + PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), |
| PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), |
| PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), |
| PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), |
