| From d0414fdd58eb51ffd6528280fd66705123663964 Mon Sep 17 00:00:00 2001 |
| From: Huibin Hong <huibin.hong@rock-chips.com> |
| Date: Fri, 6 Jul 2018 16:03:57 +0800 |
| Subject: arm64: dts: rockchip: corrected uart1 clock-names for rk3328 |
| |
| From: Huibin Hong <huibin.hong@rock-chips.com> |
| |
| commit d0414fdd58eb51ffd6528280fd66705123663964 upstream. |
| |
| Corrected the uart clock-names or the uart driver might fail. |
| |
| Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> |
| Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi |
| +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi |
| @@ -331,7 +331,7 @@ |
| reg = <0x0 0xff120000 0x0 0x100>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; |
| - clock-names = "sclk_uart", "pclk_uart"; |
| + clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac 4>, <&dmac 5>; |
| #dma-cells = <2>; |
| pinctrl-names = "default"; |
