| From a64ad008980c65d38e6cf6858429c78e6b740c41 Mon Sep 17 00:00:00 2001 |
| From: Alberto Panizzo <alberto@amarulasolutions.com> |
| Date: Fri, 6 Jul 2018 15:18:51 +0200 |
| Subject: clk: rockchip: fix clk_i2sout parent selection bits on rk3399 |
| |
| From: Alberto Panizzo <alberto@amarulasolutions.com> |
| |
| commit a64ad008980c65d38e6cf6858429c78e6b740c41 upstream. |
| |
| Register, shift and mask were wrong according to datasheet. |
| |
| Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com> |
| Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com> |
| Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/rockchip/clk-rk3399.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/clk/rockchip/clk-rk3399.c |
| +++ b/drivers/clk/rockchip/clk-rk3399.c |
| @@ -630,7 +630,7 @@ static struct rockchip_clk_branch rk3399 |
| MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, |
| RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), |
| COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, |
| - RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, |
| + RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, |
| RK3399_CLKGATE_CON(8), 12, GFLAGS), |
| |
| /* uart */ |
