| From 1b1f01b653b408ebe58fec78c566d1075d285c64 Mon Sep 17 00:00:00 2001 |
| From: Florian Fainelli <f.fainelli@gmail.com> |
| Date: Thu, 9 May 2019 11:30:47 -0700 |
| Subject: MIPS: perf: Fix build with CONFIG_CPU_BMIPS5000 enabled |
| |
| From: Florian Fainelli <f.fainelli@gmail.com> |
| |
| commit 1b1f01b653b408ebe58fec78c566d1075d285c64 upstream. |
| |
| arch/mips/kernel/perf_event_mipsxx.c: In function 'mipsxx_pmu_enable_event': |
| arch/mips/kernel/perf_event_mipsxx.c:326:21: error: unused variable 'event' [-Werror=unused-variable] |
| struct perf_event *event = container_of(evt, struct perf_event, hw); |
| ^~~~~ |
| |
| Fix this by making use of IS_ENABLED() to simplify the code and avoid |
| unnecessary ifdefery. |
| |
| Fixes: 84002c88599d ("MIPS: perf: Fix perf with MT counting other threads") |
| Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
| Signed-off-by: Paul Burton <paul.burton@mips.com> |
| Cc: linux-mips@linux-mips.org |
| Cc: Peter Zijlstra <peterz@infradead.org> |
| Cc: Ingo Molnar <mingo@redhat.com> |
| Cc: Arnaldo Carvalho de Melo <acme@kernel.org> |
| Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| Cc: Jiri Olsa <jolsa@redhat.com> |
| Cc: Namhyung Kim <namhyung@kernel.org> |
| Cc: Ralf Baechle <ralf@linux-mips.org> |
| Cc: James Hogan <jhogan@kernel.org> |
| Cc: linux-kernel@vger.kernel.org |
| Cc: linux-mips@vger.kernel.org |
| Cc: stable@vger.kernel.org # v4.18+ |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/mips/kernel/perf_event_mipsxx.c | 21 +++------------------ |
| 1 file changed, 3 insertions(+), 18 deletions(-) |
| |
| --- a/arch/mips/kernel/perf_event_mipsxx.c |
| +++ b/arch/mips/kernel/perf_event_mipsxx.c |
| @@ -64,17 +64,11 @@ struct mips_perf_event { |
| #define CNTR_EVEN 0x55555555 |
| #define CNTR_ODD 0xaaaaaaaa |
| #define CNTR_ALL 0xffffffff |
| -#ifdef CONFIG_MIPS_MT_SMP |
| enum { |
| T = 0, |
| V = 1, |
| P = 2, |
| } range; |
| -#else |
| - #define T |
| - #define V |
| - #define P |
| -#endif |
| }; |
| |
| static struct mips_perf_event raw_event; |
| @@ -325,9 +319,7 @@ static void mipsxx_pmu_enable_event(stru |
| { |
| struct perf_event *event = container_of(evt, struct perf_event, hw); |
| struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| -#ifdef CONFIG_MIPS_MT_SMP |
| unsigned int range = evt->event_base >> 24; |
| -#endif /* CONFIG_MIPS_MT_SMP */ |
| |
| WARN_ON(idx < 0 || idx >= mipspmu.num_counters); |
| |
| @@ -336,21 +328,15 @@ static void mipsxx_pmu_enable_event(stru |
| /* Make sure interrupt enabled. */ |
| MIPS_PERFCTRL_IE; |
| |
| -#ifdef CONFIG_CPU_BMIPS5000 |
| - { |
| + if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) { |
| /* enable the counter for the calling thread */ |
| cpuc->saved_ctrl[idx] |= |
| (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC; |
| - } |
| -#else |
| -#ifdef CONFIG_MIPS_MT_SMP |
| - if (range > V) { |
| + } else if (IS_ENABLED(CONFIG_MIPS_MT_SMP) && range > V) { |
| /* The counter is processor wide. Set it up to count all TCs. */ |
| pr_debug("Enabling perf counter for all TCs\n"); |
| cpuc->saved_ctrl[idx] |= M_TC_EN_ALL; |
| - } else |
| -#endif /* CONFIG_MIPS_MT_SMP */ |
| - { |
| + } else { |
| unsigned int cpu, ctrl; |
| |
| /* |
| @@ -365,7 +351,6 @@ static void mipsxx_pmu_enable_event(stru |
| cpuc->saved_ctrl[idx] |= ctrl; |
| pr_debug("Enabling perf counter for CPU%d\n", cpu); |
| } |
| -#endif /* CONFIG_CPU_BMIPS5000 */ |
| /* |
| * We do not actually let the counter run. Leave it until start(). |
| */ |