| From 831adffb3b7b8df4c8e20b7b00843129fb87a166 Mon Sep 17 00:00:00 2001 |
| From: Jernej Skrabec <jernej.skrabec@siol.net> |
| Date: Tue, 14 May 2019 22:43:37 +0200 |
| Subject: drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHz |
| |
| From: Jernej Skrabec <jernej.skrabec@siol.net> |
| |
| commit 831adffb3b7b8df4c8e20b7b00843129fb87a166 upstream. |
| |
| Vendor provided documentation says that EMP bits should be set to 3 for |
| pixel clocks greater than 148.5 MHz. |
| |
| Fix that. |
| |
| Cc: stable@vger.kernel.org # 4.17+ |
| Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") |
| Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> |
| Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20190514204337.11068-3-jernej.skrabec@siol.net |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 ++- |
| 1 file changed, 2 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c |
| +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c |
| @@ -177,7 +177,8 @@ static int sun8i_hdmi_phy_config_h3(stru |
| SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | |
| SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4); |
| ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) | |
| - SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13); |
| + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) | |
| + SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3); |
| } |
| |
| regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, |
