| From a04e23d42a1ce5d5f421692bb1c7e9352832819d Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Tue, 26 Apr 2016 19:46:32 +0300 |
| Subject: drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency |
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| |
| From: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| |
| commit a04e23d42a1ce5d5f421692bb1c7e9352832819d upstream. |
| |
| Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure |
| if this is a late addition to the spec, or if I simply overlooked this |
| step when writing the original code. |
| |
| This is what Bspec has to say about CDCLK_FREQ: |
| "Program this field to the CD clock frequency minus one. This is used to |
| generate a divided down clock for miscellaneous timers in display." |
| |
| And the "Broadwell Sequences for Changing CD Clock Frequency" section |
| clarifies this further: |
| "For CD clock 337.5 MHz, program 337 decimal. |
| For CD clock 450 MHz, program 449 decimal. |
| For CD clock 540 MHz, program 539 decimal. |
| For CD clock 675 MHz, program 674 decimal." |
| |
| Cc: stable@vger.kernel.org |
| Cc: Mika Kahola <mika.kahola@intel.com> |
| Fixes: b432e5cfd5e9 ("drm/i915: BDW clock change support") |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com |
| Reviewed-by: Mika Kahola <mika.kahola@intel.com> |
| (cherry picked from commit 7f1052a8fa38df635ab0dc0e6025b64ab9834824) |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| |
| --- |
| drivers/gpu/drm/i915/i915_reg.h | 2 ++ |
| drivers/gpu/drm/i915/intel_display.c | 2 ++ |
| 2 files changed, 4 insertions(+) |
| |
| --- a/drivers/gpu/drm/i915/i915_reg.h |
| +++ b/drivers/gpu/drm/i915/i915_reg.h |
| @@ -7357,6 +7357,8 @@ enum skl_disp_power_wells { |
| #define TRANS_CLK_SEL_DISABLED (0x0<<29) |
| #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) |
| |
| +#define CDCLK_FREQ 0x46200 |
| + |
| #define TRANSA_MSA_MISC 0x60410 |
| #define TRANSB_MSA_MISC 0x61410 |
| #define TRANSC_MSA_MISC 0x62410 |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -9689,6 +9689,8 @@ static void broadwell_set_cdclk(struct d |
| sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); |
| mutex_unlock(&dev_priv->rps.hw_lock); |
| |
| + I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
| + |
| intel_update_cdclk(dev); |
| |
| WARN(cdclk != dev_priv->cdclk_freq, |
