| From c7103f650a11328f28b9fa1c95027db331b7774b Mon Sep 17 00:00:00 2001 |
| From: Tony Luck <tony.luck@intel.com> |
| Date: Tue, 31 May 2016 11:50:28 -0700 |
| Subject: EDAC, sb_edac: Fix rank lookup on Broadwell |
| |
| From: Tony Luck <tony.luck@intel.com> |
| |
| commit c7103f650a11328f28b9fa1c95027db331b7774b upstream. |
| |
| Broadwell made a small change to the rank target register moving the |
| target rank ID field up from bits 16:19 to bits 20:23. |
| |
| Also found that the offset field grew by one bit in the IVY_BRIDGE to |
| HASWELL transition, so fix the RIR_OFFSET() macro too. |
| |
| Signed-off-by: Tony Luck <tony.luck@intel.com> |
| Cc: Aristeu Rozanski <arozansk@redhat.com> |
| Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> |
| Cc: linux-edac <linux-edac@vger.kernel.org> |
| Link: http://lkml.kernel.org/r/2943fb819b1f7e396681165db9c12bb3df0e0b16.1464735623.git.tony.luck@intel.com |
| Signed-off-by: Borislav Petkov <bp@suse.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/edac/sb_edac.c | 13 ++++++++----- |
| 1 file changed, 8 insertions(+), 5 deletions(-) |
| |
| --- a/drivers/edac/sb_edac.c |
| +++ b/drivers/edac/sb_edac.c |
| @@ -218,8 +218,11 @@ static const u32 rir_offset[MAX_RIR_RANG |
| { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, |
| }; |
| |
| -#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) |
| -#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) |
| +#define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ |
| + GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) |
| + |
| +#define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ |
| + GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) |
| |
| /* Device 16, functions 2-7 */ |
| |
| @@ -1175,14 +1178,14 @@ static void get_memory_layout(const stru |
| pci_read_config_dword(pvt->pci_tad[i], |
| rir_offset[j][k], |
| ®); |
| - tmp_mb = RIR_OFFSET(reg) << 6; |
| + tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; |
| |
| gb = div_u64_rem(tmp_mb, 1024, &mb); |
| edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
| i, j, k, |
| gb, (mb*1000)/1024, |
| ((u64)tmp_mb) << 20L, |
| - (u32)RIR_RNK_TGT(reg), |
| + (u32)RIR_RNK_TGT(pvt->info.type, reg), |
| reg); |
| } |
| } |
| @@ -1512,7 +1515,7 @@ static int get_memory_error_data(struct |
| pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
| rir_offset[n_rir][idx], |
| ®); |
| - *rank = RIR_RNK_TGT(reg); |
| + *rank = RIR_RNK_TGT(pvt->info.type, reg); |
| |
| edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
| n_rir, |