| From foo@baz Wed Aug 22 09:42:09 CEST 2018 |
| From: Daniel Mack <daniel@zonque.org> |
| Date: Fri, 6 Jul 2018 22:15:00 +0200 |
| Subject: ARM: pxa: irq: fix handling of ICMR registers in suspend/resume |
| |
| From: Daniel Mack <daniel@zonque.org> |
| |
| [ Upstream commit 0c1049dcb4ceec640d8bd797335bcbebdcab44d2 ] |
| |
| PXA3xx platforms have 56 interrupts that are stored in two ICMR |
| registers. The code in pxa_irq_suspend() and pxa_irq_resume() however |
| does a simple division by 32 which only leads to one register being |
| saved at suspend and restored at resume time. The NAND interrupt |
| setting, for instance, is lost. |
| |
| Fix this by using DIV_ROUND_UP() instead. |
| |
| Signed-off-by: Daniel Mack <daniel@zonque.org> |
| Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/arm/mach-pxa/irq.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/arch/arm/mach-pxa/irq.c |
| +++ b/arch/arm/mach-pxa/irq.c |
| @@ -185,7 +185,7 @@ static int pxa_irq_suspend(void) |
| { |
| int i; |
| |
| - for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
| + for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) { |
| void __iomem *base = irq_base(i); |
| |
| saved_icmr[i] = __raw_readl(base + ICMR); |
| @@ -204,7 +204,7 @@ static void pxa_irq_resume(void) |
| { |
| int i; |
| |
| - for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
| + for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) { |
| void __iomem *base = irq_base(i); |
| |
| __raw_writel(saved_icmr[i], base + ICMR); |