| From 7797167ffde1f00446301cb22b37b7c03194cfaf Mon Sep 17 00:00:00 2001 |
| From: John David Anglin <dave.anglin@bell.net> |
| Date: Sun, 12 Aug 2018 16:38:03 -0400 |
| Subject: parisc: Remove ordered stores from syscall.S |
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| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: John David Anglin <dave.anglin@bell.net> |
| |
| commit 7797167ffde1f00446301cb22b37b7c03194cfaf upstream. |
| |
| Now that we use a sync prior to releasing the locks in syscall.S, we don't need |
| the PA 2.0 ordered stores used to release some locks. Using an ordered store, |
| potentially slows the release and subsequent code. |
| |
| There are a number of other ordered stores and loads that serve no purpose. I |
| have converted these to normal stores. |
| |
| Signed-off-by: John David Anglin <dave.anglin@bell.net> |
| Cc: stable@vger.kernel.org # 4.0+ |
| Signed-off-by: Helge Deller <deller@gmx.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/parisc/kernel/syscall.S | 24 ++++++++++++------------ |
| 1 file changed, 12 insertions(+), 12 deletions(-) |
| |
| --- a/arch/parisc/kernel/syscall.S |
| +++ b/arch/parisc/kernel/syscall.S |
| @@ -629,12 +629,12 @@ cas_action: |
| stw %r1, 4(%sr2,%r20) |
| #endif |
| /* The load and store could fail */ |
| -1: ldw,ma 0(%r26), %r28 |
| +1: ldw 0(%r26), %r28 |
| sub,<> %r28, %r25, %r0 |
| -2: stw,ma %r24, 0(%r26) |
| +2: stw %r24, 0(%r26) |
| /* Free lock */ |
| sync |
| - stw,ma %r20, 0(%sr2,%r20) |
| + stw %r20, 0(%sr2,%r20) |
| #if ENABLE_LWS_DEBUG |
| /* Clear thread register indicator */ |
| stw %r0, 4(%sr2,%r20) |
| @@ -798,30 +798,30 @@ cas2_action: |
| ldo 1(%r0),%r28 |
| |
| /* 8bit CAS */ |
| -13: ldb,ma 0(%r26), %r29 |
| +13: ldb 0(%r26), %r29 |
| sub,= %r29, %r25, %r0 |
| b,n cas2_end |
| -14: stb,ma %r24, 0(%r26) |
| +14: stb %r24, 0(%r26) |
| b cas2_end |
| copy %r0, %r28 |
| nop |
| nop |
| |
| /* 16bit CAS */ |
| -15: ldh,ma 0(%r26), %r29 |
| +15: ldh 0(%r26), %r29 |
| sub,= %r29, %r25, %r0 |
| b,n cas2_end |
| -16: sth,ma %r24, 0(%r26) |
| +16: sth %r24, 0(%r26) |
| b cas2_end |
| copy %r0, %r28 |
| nop |
| nop |
| |
| /* 32bit CAS */ |
| -17: ldw,ma 0(%r26), %r29 |
| +17: ldw 0(%r26), %r29 |
| sub,= %r29, %r25, %r0 |
| b,n cas2_end |
| -18: stw,ma %r24, 0(%r26) |
| +18: stw %r24, 0(%r26) |
| b cas2_end |
| copy %r0, %r28 |
| nop |
| @@ -829,10 +829,10 @@ cas2_action: |
| |
| /* 64bit CAS */ |
| #ifdef CONFIG_64BIT |
| -19: ldd,ma 0(%r26), %r29 |
| +19: ldd 0(%r26), %r29 |
| sub,*= %r29, %r25, %r0 |
| b,n cas2_end |
| -20: std,ma %r24, 0(%r26) |
| +20: std %r24, 0(%r26) |
| copy %r0, %r28 |
| #else |
| /* Compare first word */ |
| @@ -851,7 +851,7 @@ cas2_action: |
| cas2_end: |
| /* Free lock */ |
| sync |
| - stw,ma %r20, 0(%sr2,%r20) |
| + stw %r20, 0(%sr2,%r20) |
| /* Enable interrupts */ |
| ssm PSW_SM_I, %r0 |
| /* Return to userspace, set no error */ |
