| From foo@baz Sat Nov 10 11:24:34 PST 2018 |
| From: "David S. Miller" <davem@davemloft.net> |
| Date: Fri, 12 Oct 2018 10:31:58 -0700 |
| Subject: sparc: Fix single-pcr perf event counter management. |
| |
| From: "David S. Miller" <davem@davemloft.net> |
| |
| [ Upstream commit cfdc3170d214046b9509183fe9b9544dc644d40b ] |
| |
| It is important to clear the hw->state value for non-stopped events |
| when they are added into the PMU. Otherwise when the event is |
| scheduled out, we won't read the counter because HES_UPTODATE is still |
| set. This breaks 'perf stat' and similar use cases, causing all the |
| events to show zero. |
| |
| This worked for multi-pcr because we make explicit sparc_pmu_start() |
| calls in calculate_multiple_pcrs(). calculate_single_pcr() doesn't do |
| this because the idea there is to accumulate all of the counter |
| settings into the single pcr value. So we have to add explicit |
| hw->state handling there. |
| |
| Like x86, we use the PERF_HES_ARCH bit to track truly stopped events |
| so that we don't accidently start them on a reload. |
| |
| Related to all of this, sparc_pmu_start() is missing a userpage update |
| so add it. |
| |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/sparc/kernel/perf_event.c | 17 +++++++++++++---- |
| 1 file changed, 13 insertions(+), 4 deletions(-) |
| |
| --- a/arch/sparc/kernel/perf_event.c |
| +++ b/arch/sparc/kernel/perf_event.c |
| @@ -926,6 +926,8 @@ static void read_in_all_counters(struct |
| sparc_perf_event_update(cp, &cp->hw, |
| cpuc->current_idx[i]); |
| cpuc->current_idx[i] = PIC_NO_INDEX; |
| + if (cp->hw.state & PERF_HES_STOPPED) |
| + cp->hw.state |= PERF_HES_ARCH; |
| } |
| } |
| } |
| @@ -958,10 +960,12 @@ static void calculate_single_pcr(struct |
| |
| enc = perf_event_get_enc(cpuc->events[i]); |
| cpuc->pcr[0] &= ~mask_for_index(idx); |
| - if (hwc->state & PERF_HES_STOPPED) |
| + if (hwc->state & PERF_HES_ARCH) { |
| cpuc->pcr[0] |= nop_for_index(idx); |
| - else |
| + } else { |
| cpuc->pcr[0] |= event_encoding(enc, idx); |
| + hwc->state = 0; |
| + } |
| } |
| out: |
| cpuc->pcr[0] |= cpuc->event[0]->hw.config_base; |
| @@ -987,6 +991,9 @@ static void calculate_multiple_pcrs(stru |
| |
| cpuc->current_idx[i] = idx; |
| |
| + if (cp->hw.state & PERF_HES_ARCH) |
| + continue; |
| + |
| sparc_pmu_start(cp, PERF_EF_RELOAD); |
| } |
| out: |
| @@ -1078,6 +1085,8 @@ static void sparc_pmu_start(struct perf_ |
| event->hw.state = 0; |
| |
| sparc_pmu_enable_event(cpuc, &event->hw, idx); |
| + |
| + perf_event_update_userpage(event); |
| } |
| |
| static void sparc_pmu_stop(struct perf_event *event, int flags) |
| @@ -1370,9 +1379,9 @@ static int sparc_pmu_add(struct perf_eve |
| cpuc->events[n0] = event->hw.event_base; |
| cpuc->current_idx[n0] = PIC_NO_INDEX; |
| |
| - event->hw.state = PERF_HES_UPTODATE; |
| + event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
| if (!(ef_flags & PERF_EF_START)) |
| - event->hw.state |= PERF_HES_STOPPED; |
| + event->hw.state |= PERF_HES_ARCH; |
| |
| /* |
| * If group events scheduling transaction was started, |