| From foo@baz Thu Nov 9 09:48:01 CET 2017 |
| From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| Date: Wed, 11 Jan 2017 16:43:32 +0200 |
| Subject: serial: sh-sci: Fix register offsets for the IRDA serial port |
| |
| From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| |
| |
| [ Upstream commit a752ba18af8285e3eeda572f40dddaebff0c3621 ] |
| |
| Even though most of its registers are 8-bit wide, the IRDA has two |
| 16-bit registers that make it a 16-bit peripheral and not a 8-bit |
| peripheral with addresses shifted by one. Fix the registers offset in |
| the driver and the platform data regshift value. |
| |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| Signed-off-by: Sasha Levin <alexander.levin@verizon.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/sh/kernel/cpu/sh3/setup-sh770x.c | 1 - |
| drivers/tty/serial/sh-sci.c | 17 ++++++++--------- |
| 2 files changed, 8 insertions(+), 10 deletions(-) |
| |
| --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c |
| +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c |
| @@ -165,7 +165,6 @@ static struct plat_sci_port scif2_platfo |
| .scscr = SCSCR_TE | SCSCR_RE, |
| .type = PORT_IRDA, |
| .ops = &sh770x_sci_port_ops, |
| - .regshift = 1, |
| }; |
| |
| static struct resource scif2_resources[] = { |
| --- a/drivers/tty/serial/sh-sci.c |
| +++ b/drivers/tty/serial/sh-sci.c |
| @@ -193,18 +193,17 @@ static const struct plat_sci_reg sci_reg |
| }, |
| |
| /* |
| - * Common definitions for legacy IrDA ports, dependent on |
| - * regshift value. |
| + * Common definitions for legacy IrDA ports. |
| */ |
| [SCIx_IRDA_REGTYPE] = { |
| [SCSMR] = { 0x00, 8 }, |
| - [SCBRR] = { 0x01, 8 }, |
| - [SCSCR] = { 0x02, 8 }, |
| - [SCxTDR] = { 0x03, 8 }, |
| - [SCxSR] = { 0x04, 8 }, |
| - [SCxRDR] = { 0x05, 8 }, |
| - [SCFCR] = { 0x06, 8 }, |
| - [SCFDR] = { 0x07, 16 }, |
| + [SCBRR] = { 0x02, 8 }, |
| + [SCSCR] = { 0x04, 8 }, |
| + [SCxTDR] = { 0x06, 8 }, |
| + [SCxSR] = { 0x08, 16 }, |
| + [SCxRDR] = { 0x0a, 8 }, |
| + [SCFCR] = { 0x0c, 8 }, |
| + [SCFDR] = { 0x0e, 16 }, |
| [SCTFDR] = sci_reg_invalid, |
| [SCRFDR] = sci_reg_invalid, |
| [SCSPTR] = sci_reg_invalid, |
