| From 30750927e1ffde90d7ddbd3e630cf7d03068575e Mon Sep 17 00:00:00 2001 |
| From: Douglas Anderson <dianders@chromium.org> |
| Date: Tue, 9 Apr 2019 13:47:06 -0700 |
| Subject: clk: rockchip: Make rkpwm a critical clock on rk3288 |
| |
| [ Upstream commit dfe7fb21cd9e730230d55a79bc72cf2ece67cdd5 ] |
| |
| Most rk3288-based boards are derived from the EVB and thus use a PWM |
| regulator for the logic rail. However, most rk3288-based boards don't |
| specify the PWM regulator in their device tree. We'll deal with that |
| by making it critical. |
| |
| NOTE: it's important to make it critical and not just IGNORE_UNUSED |
| because all PWMs in the system share the same clock. We don't want |
| another PWM user to turn the clock on and off and kill the logic rail. |
| |
| This change is in preparation for actually having the PWMs in the |
| rk3288 device tree actually point to the proper PWM clock. Up until |
| now they've all pointed to the clock for the old IP block and they've |
| all worked due to the fact that rkpwm was IGNORE_UNUSED and that the |
| clock rates for both clocks were the same. |
| |
| Signed-off-by: Douglas Anderson <dianders@chromium.org> |
| Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/rockchip/clk-rk3288.c | 4 +++- |
| 1 file changed, 3 insertions(+), 1 deletion(-) |
| |
| diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c |
| index 623c5f684987c..355d6a3611dbf 100644 |
| --- a/drivers/clk/rockchip/clk-rk3288.c |
| +++ b/drivers/clk/rockchip/clk-rk3288.c |
| @@ -697,7 +697,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { |
| GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), |
| GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), |
| GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), |
| - GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), |
| + GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS), |
| |
| /* ddrctrl [DDR Controller PHY clock] gates */ |
| GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS), |
| @@ -838,6 +838,8 @@ static const char *const rk3288_critical_clocks[] __initconst = { |
| "pclk_pd_pmu", |
| "pclk_pmu_niu", |
| "pmu_hclk_otg0", |
| + /* pwm-regulators on some boards, so handoff-critical later */ |
| + "pclk_rkpwm", |
| }; |
| |
| static void __iomem *rk3288_cru_base; |
| -- |
| 2.20.1 |
| |