| From 06e1624fc6696050c5c1b24240609c8ab2104075 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 6 Apr 2021 17:53:46 +0100 |
| Subject: net/mlx5: Fix bit-wise and with zero |
| |
| From: Colin Ian King <colin.king@canonical.com> |
| |
| [ Upstream commit 82c3ba31c370b6001cbf90689e98da1fb6f26aef ] |
| |
| The bit-wise and of the action field with MLX5_ACCEL_ESP_ACTION_DECRYPT |
| is incorrect as MLX5_ACCEL_ESP_ACTION_DECRYPT is zero and not intended |
| to be a bit-flag. Fix this by using the == operator as was originally |
| intended. |
| |
| Addresses-Coverity: ("Logically dead code") |
| Fixes: 7dfee4b1d79e ("net/mlx5: IPsec, Refactor SA handle creation and destruction") |
| Signed-off-by: Colin Ian King <colin.king@canonical.com> |
| Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c |
| index cc67366495b0..bed154e9a1ef 100644 |
| --- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c |
| +++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c |
| @@ -850,7 +850,7 @@ mlx5_fpga_ipsec_release_sa_ctx(struct mlx5_fpga_ipsec_sa_ctx *sa_ctx) |
| return; |
| } |
| |
| - if (sa_ctx->fpga_xfrm->accel_xfrm.attrs.action & |
| + if (sa_ctx->fpga_xfrm->accel_xfrm.attrs.action == |
| MLX5_ACCEL_ESP_ACTION_DECRYPT) |
| ida_simple_remove(&fipsec->halloc, sa_ctx->sa_handle); |
| |
| -- |
| 2.30.2 |
| |
