| From 303dbe92835713a9206bcd31411af8a13af964cb Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 5 Mar 2021 11:11:04 +0530 |
| Subject: arm64: dts: ti: k3-j721e-main: Update the speed modes supported and |
| their itap delay values for MMCSD subsystems |
| |
| From: Aswath Govindraju <a-govindraju@ti.com> |
| |
| [ Upstream commit eb8f6194e8074d7b00642dd75cf04d13e1b218e4 ] |
| |
| According to latest errata of J721e [1], HS400 mode is not supported |
| in MMCSD0 subsystem (i2024) and SDR104 mode is not supported in MMCSD1/2 |
| subsystems (i2090). Therefore, replace mmc-hs400-1_8v with mmc-hs200-1_8v |
| in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode. |
| |
| Also, update the itap delay values for all the MMCSD subsystems according |
| the latest J721e data sheet[2] |
| |
| [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf |
| [2] - https://www.ti.com/lit/ds/symlink/tda4vm.pdf |
| |
| Fixes: cd48ce86a4d0 ("arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes") |
| Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
| Signed-off-by: Nishanth Menon <nm@ti.com> |
| Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> |
| Link: https://lore.kernel.org/r/20210305054104.10153-1-a-govindraju@ti.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 17 ++++++++++++++++- |
| 1 file changed, 16 insertions(+), 1 deletion(-) |
| |
| diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi |
| index b32df591c766..91802e1502dd 100644 |
| --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi |
| +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi |
| @@ -1078,13 +1078,16 @@ |
| assigned-clocks = <&k3_clks 91 1>; |
| assigned-clock-parents = <&k3_clks 91 2>; |
| bus-width = <8>; |
| - mmc-hs400-1_8v; |
| + mmc-hs200-1_8v; |
| mmc-ddr-1_8v; |
| ti,otap-del-sel-legacy = <0xf>; |
| ti,otap-del-sel-mmc-hs = <0xf>; |
| ti,otap-del-sel-ddr52 = <0x5>; |
| ti,otap-del-sel-hs200 = <0x6>; |
| ti,otap-del-sel-hs400 = <0x0>; |
| + ti,itap-del-sel-legacy = <0x10>; |
| + ti,itap-del-sel-mmc-hs = <0xa>; |
| + ti,itap-del-sel-ddr52 = <0x3>; |
| ti,trm-icp = <0x8>; |
| ti,strobe-sel = <0x77>; |
| dma-coherent; |
| @@ -1105,9 +1108,15 @@ |
| ti,otap-del-sel-sdr25 = <0xf>; |
| ti,otap-del-sel-sdr50 = <0xc>; |
| ti,otap-del-sel-ddr50 = <0xc>; |
| + ti,itap-del-sel-legacy = <0x0>; |
| + ti,itap-del-sel-sd-hs = <0x0>; |
| + ti,itap-del-sel-sdr12 = <0x0>; |
| + ti,itap-del-sel-sdr25 = <0x0>; |
| + ti,itap-del-sel-ddr50 = <0x2>; |
| ti,trm-icp = <0x8>; |
| ti,clkbuf-sel = <0x7>; |
| dma-coherent; |
| + sdhci-caps-mask = <0x2 0x0>; |
| }; |
| |
| main_sdhci2: sdhci@4f98000 { |
| @@ -1125,9 +1134,15 @@ |
| ti,otap-del-sel-sdr25 = <0xf>; |
| ti,otap-del-sel-sdr50 = <0xc>; |
| ti,otap-del-sel-ddr50 = <0xc>; |
| + ti,itap-del-sel-legacy = <0x0>; |
| + ti,itap-del-sel-sd-hs = <0x0>; |
| + ti,itap-del-sel-sdr12 = <0x0>; |
| + ti,itap-del-sel-sdr25 = <0x0>; |
| + ti,itap-del-sel-ddr50 = <0x2>; |
| ti,trm-icp = <0x8>; |
| ti,clkbuf-sel = <0x7>; |
| dma-coherent; |
| + sdhci-caps-mask = <0x2 0x0>; |
| }; |
| |
| usbss0: cdns-usb@4104000 { |
| -- |
| 2.30.2 |
| |
