| From 623e0da67669e57fa539cf0095220ff658a8e710 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 8 Apr 2021 13:42:18 +0200 |
| Subject: clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz |
| to 1 GHz |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Pali Rohár <pali@kernel.org> |
| |
| [ Upstream commit 4decb9187589f61fe9fc2bc4d9b01160b0a610c5 ] |
| |
| It was observed that the workaround introduced by commit 61c40f35f5cd |
| ("clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to |
| 1.2GHz") when base CPU frequency is 1.2 GHz is also required when base |
| CPU frequency is 1 GHz. Otherwise switching CPU frequency directly from |
| L2 (250 MHz) to L0 (1 GHz) causes a crash. |
| |
| When base CPU frequency is just 800 MHz no crashed were observed during |
| switch from L2 to L0. |
| |
| Signed-off-by: Pali Rohár <pali@kernel.org> |
| Acked-by: Stephen Boyd <sboyd@kernel.org> |
| Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> |
| Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> |
| Tested-by: Anders Trier Olesen <anders.trier.olesen@gmail.com> |
| Tested-by: Philip Soares <philips@netisense.com> |
| Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") |
| Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/mvebu/armada-37xx-periph.c | 12 +++++++----- |
| 1 file changed, 7 insertions(+), 5 deletions(-) |
| |
| diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c |
| index 6507bd2c5f31..b15e177bea7e 100644 |
| --- a/drivers/clk/mvebu/armada-37xx-periph.c |
| +++ b/drivers/clk/mvebu/armada-37xx-periph.c |
| @@ -487,8 +487,10 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate, |
| } |
| |
| /* |
| - * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz |
| - * respectively) to L0 frequency (1.2 Ghz) requires a significant |
| + * Workaround when base CPU frequnecy is 1000 or 1200 MHz |
| + * |
| + * Switching the CPU from the L2 or L3 frequencies (250/300 or 200 MHz |
| + * respectively) to L0 frequency (1/1.2 GHz) requires a significant |
| * amount of time to let VDD stabilize to the appropriate |
| * voltage. This amount of time is large enough that it cannot be |
| * covered by the hardware countdown register. Due to this, the CPU |
| @@ -498,15 +500,15 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate, |
| * To work around this problem, we prevent switching directly from the |
| * L2/L3 frequencies to the L0 frequency, and instead switch to the L1 |
| * frequency in-between. The sequence therefore becomes: |
| - * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ) |
| + * 1. First switch from L2/L3 (200/250/300 MHz) to L1 (500/600 MHz) |
| * 2. Sleep 20ms for stabling VDD voltage |
| - * 3. Then switch from L1(600MHZ) to L0(1200Mhz). |
| + * 3. Then switch from L1 (500/600 MHz) to L0 (1000/1200 MHz). |
| */ |
| static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base) |
| { |
| unsigned int cur_level; |
| |
| - if (rate != 1200 * 1000 * 1000) |
| + if (rate < 1000 * 1000 * 1000) |
| return; |
| |
| regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level); |
| -- |
| 2.30.2 |
| |