| From eccf34250eed72ddb56a4c5ec236b2a1aaa65174 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 6 Apr 2021 23:40:15 +0800 |
| Subject: clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback |
| |
| From: Quanyang Wang <quanyang.wang@windriver.com> |
| |
| [ Upstream commit d7fd3f9f53df8bb2212dff70f66f12cae0e1a653 ] |
| |
| The round_rate callback should only perform rate calculation and not |
| involve calling zynqmp_pll_set_mode to change the pll mode. So let's |
| move zynqmp_pll_set_mode out of round_rate and to set_rate callback. |
| |
| Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") |
| Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> |
| Link: https://lore.kernel.org/r/20210406154015.602779-1-quanyang.wang@windriver.com |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/zynqmp/pll.c | 12 ++++++------ |
| 1 file changed, 6 insertions(+), 6 deletions(-) |
| |
| diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c |
| index 92f449ed38e5..03bfe62c1e62 100644 |
| --- a/drivers/clk/zynqmp/pll.c |
| +++ b/drivers/clk/zynqmp/pll.c |
| @@ -100,9 +100,7 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
| /* Enable the fractional mode if needed */ |
| rate_div = (rate * FRAC_DIV) / *prate; |
| f = rate_div % FRAC_DIV; |
| - zynqmp_pll_set_mode(hw, !!f); |
| - |
| - if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { |
| + if (f) { |
| if (rate > PS_PLL_VCO_MAX) { |
| fbdiv = rate / PS_PLL_VCO_MAX; |
| rate = rate / (fbdiv + 1); |
| @@ -173,10 +171,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
| long rate_div, frac, m, f; |
| int ret; |
| |
| - if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { |
| - rate_div = (rate * FRAC_DIV) / parent_rate; |
| + rate_div = (rate * FRAC_DIV) / parent_rate; |
| + f = rate_div % FRAC_DIV; |
| + zynqmp_pll_set_mode(hw, !!f); |
| + |
| + if (f) { |
| m = rate_div / FRAC_DIV; |
| - f = rate_div % FRAC_DIV; |
| m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX)); |
| rate = parent_rate * m; |
| frac = (parent_rate * f) / FRAC_DIV; |
| -- |
| 2.30.2 |
| |