| From c3567f8a359b7917dcffa442301f88ed0a75211f Mon Sep 17 00:00:00 2001 |
| From: Noam Camus <noamc@ezchip.com> |
| Date: Thu, 12 Sep 2013 13:07:39 +0530 |
| Subject: ARC: SMP failed to boot due to missing IVT setup |
| |
| From: Noam Camus <noamc@ezchip.com> |
| |
| commit c3567f8a359b7917dcffa442301f88ed0a75211f upstream. |
| |
| Commit 05b016ecf5e7a "ARC: Setup Vector Table Base in early boot" moved |
| the Interrupt vector Table setup out of arc_init_IRQ() which is called |
| for all CPUs, to entry point of boot cpu only, breaking booting of others. |
| |
| Fix by adding the same to entry point of non-boot CPUs too. |
| |
| read_arc_build_cfg_regs() printing IVT Base Register didn't help the |
| casue since it prints a synthetic value if zero which is totally bogus, |
| so fix that to print the exact Register. |
| |
| [vgupta: Remove the now stale comment from header of arc_init_IRQ and |
| also added the commentary for halt-on-reset] |
| |
| Cc: Gilad Ben-Yossef <gilad@benyossef.com> |
| Signed-off-by: Noam Camus <noamc@ezchip.com> |
| Signed-off-by: Vineet Gupta <vgupta@synopsys.com> |
| Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arc/include/asm/sections.h | 1 - |
| arch/arc/kernel/head.S | 5 +++++ |
| arch/arc/kernel/irq.c | 1 - |
| arch/arc/kernel/setup.c | 3 --- |
| 4 files changed, 5 insertions(+), 5 deletions(-) |
| |
| --- a/arch/arc/include/asm/sections.h |
| +++ b/arch/arc/include/asm/sections.h |
| @@ -11,7 +11,6 @@ |
| |
| #include <asm-generic/sections.h> |
| |
| -extern char _int_vec_base_lds[]; |
| extern char __arc_dccm_base[]; |
| extern char __dtb_start[]; |
| |
| --- a/arch/arc/kernel/head.S |
| +++ b/arch/arc/kernel/head.S |
| @@ -34,6 +34,9 @@ stext: |
| ; IDENTITY Reg [ 3 2 1 0 ] |
| ; (cpu-id) ^^^ => Zero for UP ARC700 |
| ; => #Core-ID if SMP (Master 0) |
| + ; Note that non-boot CPUs might not land here if halt-on-reset and |
| + ; instead breath life from @first_lines_of_secondary, but we still |
| + ; need to make sure only boot cpu takes this path. |
| GET_CPU_ID r5 |
| cmp r5, 0 |
| jnz arc_platform_smp_wait_to_boot |
| @@ -98,6 +101,8 @@ stext: |
| |
| first_lines_of_secondary: |
| |
| + sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] |
| + |
| ; setup per-cpu idle task as "current" on this CPU |
| ld r0, [@secondary_idle_tsk] |
| SET_CURR_TASK_ON_CPU r0, r1 |
| --- a/arch/arc/kernel/irq.c |
| +++ b/arch/arc/kernel/irq.c |
| @@ -24,7 +24,6 @@ |
| * -Needed for each CPU (hence not foldable into init_IRQ) |
| * |
| * what it does ? |
| - * -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000 |
| * -Disable all IRQs (on CPU side) |
| * -Optionally, setup the High priority Interrupts as Level 2 IRQs |
| */ |
| --- a/arch/arc/kernel/setup.c |
| +++ b/arch/arc/kernel/setup.c |
| @@ -47,10 +47,7 @@ void __cpuinit read_arc_build_cfg_regs(v |
| READ_BCR(AUX_IDENTITY, cpu->core); |
| |
| cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR); |
| - |
| cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); |
| - if (cpu->vec_base == 0) |
| - cpu->vec_base = (unsigned int)_int_vec_base_lds; |
| |
| READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space); |
| cpu->uncached_base = uncached_space.start << 24; |