| From foo@baz Sun 27 Oct 2019 09:50:54 AM CET |
| From: Ard Biesheuvel <ard.biesheuvel@linaro.org> |
| Date: Thu, 24 Oct 2019 14:48:27 +0200 |
| Subject: arm64: Always enable spectre-v2 vulnerability detection |
| To: stable@vger.kernel.org |
| Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>, Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Jeremy Linton <jeremy.linton@arm.com>, Andre Przywara <andre.przywara@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Stefan Wahren <stefan.wahren@i2se.com>, Will Deacon <will.deacon@arm.com> |
| Message-ID: <20191024124833.4158-43-ard.biesheuvel@linaro.org> |
| |
| From: Jeremy Linton <jeremy.linton@arm.com> |
| |
| [ Upstream commit 8c1e3d2bb44cbb998cb28ff9a18f105fee7f1eb3 ] |
| |
| Ensure we are always able to detect whether or not the CPU is affected |
| by Spectre-v2, so that we can later advertise this to userspace. |
| |
| Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> |
| Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
| Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> |
| Tested-by: Stefan Wahren <stefan.wahren@i2se.com> |
| Signed-off-by: Will Deacon <will.deacon@arm.com> |
| Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/arm64/kernel/cpu_errata.c | 15 ++++++++------- |
| 1 file changed, 8 insertions(+), 7 deletions(-) |
| |
| --- a/arch/arm64/kernel/cpu_errata.c |
| +++ b/arch/arm64/kernel/cpu_errata.c |
| @@ -76,7 +76,6 @@ cpu_enable_trap_ctr_access(const struct |
| config_sctlr_el1(SCTLR_EL1_UCT, 0); |
| } |
| |
| -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
| #include <asm/mmu_context.h> |
| #include <asm/cacheflush.h> |
| |
| @@ -217,11 +216,11 @@ static int detect_harden_bp_fw(void) |
| ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) |
| cb = qcom_link_stack_sanitization; |
| |
| - install_bp_hardening_cb(cb, smccc_start, smccc_end); |
| + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) |
| + install_bp_hardening_cb(cb, smccc_start, smccc_end); |
| |
| return 1; |
| } |
| -#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ |
| |
| DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); |
| |
| @@ -457,7 +456,6 @@ out_printmsg: |
| .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ |
| CAP_MIDR_RANGE_LIST(midr_list) |
| |
| -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
| /* |
| * List of CPUs that do not need any Spectre-v2 mitigation at all. |
| */ |
| @@ -489,6 +487,12 @@ check_branch_predictor(const struct arm6 |
| if (!need_wa) |
| return false; |
| |
| + if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) { |
| + pr_warn_once("spectrev2 mitigation disabled by kernel configuration\n"); |
| + __hardenbp_enab = false; |
| + return false; |
| + } |
| + |
| /* forced off */ |
| if (__nospectre_v2) { |
| pr_info_once("spectrev2 mitigation disabled by command line option\n"); |
| @@ -500,7 +504,6 @@ check_branch_predictor(const struct arm6 |
| |
| return (need_wa > 0); |
| } |
| -#endif |
| |
| const struct arm64_cpu_capabilities arm64_errata[] = { |
| #if defined(CONFIG_ARM64_ERRATUM_826319) || \ |
| @@ -640,13 +643,11 @@ const struct arm64_cpu_capabilities arm6 |
| ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), |
| }, |
| #endif |
| -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
| { |
| .capability = ARM64_HARDEN_BRANCH_PREDICTOR, |
| .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, |
| .matches = check_branch_predictor, |
| }, |
| -#endif |
| { |
| .desc = "Speculative Store Bypass Disable", |
| .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, |