| From a0447ef61b8d46fe801615dcf135ef0fd04e2684 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Mon, 12 Apr 2021 08:24:50 +0200 |
| Subject: ARM: dts: imx6: phyFLEX: Fix UART hardware flow control |
| |
| From: Primoz Fiser <primoz.fiser@norik.com> |
| |
| [ Upstream commit 14cdc1f243d79e0b46be150502b7dba9c5a6bdfd ] |
| |
| Serial interface uart3 on phyFLEX board is capable of 5-wire connection |
| including signals RTS and CTS for hardware flow control. |
| |
| Fix signals UART3_CTS_B and UART3_RTS_B padmux assignments and add |
| missing property "uart-has-rtscts" to allow serial interface to be |
| configured and used with the hardware flow control. |
| |
| Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> |
| Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 5 +++-- |
| 1 file changed, 3 insertions(+), 2 deletions(-) |
| |
| diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi |
| index 9499d113b139..25462f778994 100644 |
| --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi |
| +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi |
| @@ -306,8 +306,8 @@ |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 |
| - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 |
| - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 |
| + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 |
| + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 |
| >; |
| }; |
| |
| @@ -394,6 +394,7 @@ |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| + uart-has-rtscts; |
| status = "disabled"; |
| }; |
| |
| -- |
| 2.30.2 |
| |