| From 04d019961fd15de92874575536310243a0d4c5c5 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com> |
| Date: Wed, 21 Apr 2021 18:33:59 +0300 |
| Subject: drm/i915: Read C0DRB3/C1DRB3 as 16 bits again |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| |
| commit 04d019961fd15de92874575536310243a0d4c5c5 upstream. |
| |
| We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them |
| as such. |
| |
| Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences") |
| Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com |
| (cherry picked from commit f765a5b48c667bdada5e49d5e0f23f8c0687b21b) |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |
| +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c |
| @@ -652,8 +652,8 @@ static void detect_bit_6_swizzle(struct |
| * banks of memory are paired and unswizzled on the |
| * uneven portion, so leave that as unknown. |
| */ |
| - if (intel_uncore_read(uncore, C0DRB3) == |
| - intel_uncore_read(uncore, C1DRB3)) { |
| + if (intel_uncore_read16(uncore, C0DRB3) == |
| + intel_uncore_read16(uncore, C1DRB3)) { |
| swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| swizzle_y = I915_BIT_6_SWIZZLE_9; |
| } |