| From 09e57838e210a349031eea6d684f92bdc94773e2 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 23 Feb 2021 17:02:27 +1000 |
| Subject: selftests/powerpc: Fix L1D flushing tests for Power10 |
| |
| From: Russell Currey <ruscur@russell.cc> |
| |
| [ Upstream commit 3a72c94ebfb1f171eba0715998010678a09ec796 ] |
| |
| The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1 |
| perf event to count L1D misses. The value of this event has changed |
| over time: |
| |
| - Power7 uses 0x400f0 |
| - Power8 and Power9 use both 0x400f0 and 0x3e054 |
| - Power10 uses only 0x3e054 |
| |
| Rather than relying on raw values, configure perf to count L1D read |
| misses in the most explicit way available. |
| |
| This fixes the selftests to work on systems without 0x400f0 as |
| PM_LD_MISS_L1, and should change no behaviour for systems that the tests |
| already worked on. |
| |
| The only potential downside is that referring to a specific perf event |
| requires PMU support implemented in the kernel for that platform. |
| |
| Signed-off-by: Russell Currey <ruscur@russell.cc> |
| Acked-by: Daniel Axtens <dja@axtens.net> |
| Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
| Link: https://lore.kernel.org/r/20210223070227.2916871-1-ruscur@russell.cc |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| tools/testing/selftests/powerpc/security/entry_flush.c | 2 +- |
| tools/testing/selftests/powerpc/security/flush_utils.h | 4 ++++ |
| tools/testing/selftests/powerpc/security/rfi_flush.c | 2 +- |
| 3 files changed, 6 insertions(+), 2 deletions(-) |
| |
| diff --git a/tools/testing/selftests/powerpc/security/entry_flush.c b/tools/testing/selftests/powerpc/security/entry_flush.c |
| index 78cf914fa321..68ce377b205e 100644 |
| --- a/tools/testing/selftests/powerpc/security/entry_flush.c |
| +++ b/tools/testing/selftests/powerpc/security/entry_flush.c |
| @@ -53,7 +53,7 @@ int entry_flush_test(void) |
| |
| entry_flush = entry_flush_orig; |
| |
| - fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1); |
| + fd = perf_event_open_counter(PERF_TYPE_HW_CACHE, PERF_L1D_READ_MISS_CONFIG, -1); |
| FAIL_IF(fd < 0); |
| |
| p = (char *)memalign(zero_size, CACHELINE_SIZE); |
| diff --git a/tools/testing/selftests/powerpc/security/flush_utils.h b/tools/testing/selftests/powerpc/security/flush_utils.h |
| index 07a5eb301466..7a3d60292916 100644 |
| --- a/tools/testing/selftests/powerpc/security/flush_utils.h |
| +++ b/tools/testing/selftests/powerpc/security/flush_utils.h |
| @@ -9,6 +9,10 @@ |
| |
| #define CACHELINE_SIZE 128 |
| |
| +#define PERF_L1D_READ_MISS_CONFIG ((PERF_COUNT_HW_CACHE_L1D) | \ |
| + (PERF_COUNT_HW_CACHE_OP_READ << 8) | \ |
| + (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)) |
| + |
| void syscall_loop(char *p, unsigned long iterations, |
| unsigned long zero_size); |
| |
| diff --git a/tools/testing/selftests/powerpc/security/rfi_flush.c b/tools/testing/selftests/powerpc/security/rfi_flush.c |
| index 7565fd786640..f73484a6470f 100644 |
| --- a/tools/testing/selftests/powerpc/security/rfi_flush.c |
| +++ b/tools/testing/selftests/powerpc/security/rfi_flush.c |
| @@ -54,7 +54,7 @@ int rfi_flush_test(void) |
| |
| rfi_flush = rfi_flush_orig; |
| |
| - fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1); |
| + fd = perf_event_open_counter(PERF_TYPE_HW_CACHE, PERF_L1D_READ_MISS_CONFIG, -1); |
| FAIL_IF(fd < 0); |
| |
| p = (char *)memalign(zero_size, CACHELINE_SIZE); |
| -- |
| 2.30.2 |
| |