| From 817be66b059cbdf1f2f7d31b6df0f82fec86a866 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 24 Mar 2021 16:16:03 +0800 |
| Subject: iommu/arm-smmu-v3: add bit field SFM into GERROR_ERR_MASK |
| |
| From: Zhen Lei <thunder.leizhen@huawei.com> |
| |
| [ Upstream commit 655c447c97d7fe462e6cd9e15809037be028bc70 ] |
| |
| In arm_smmu_gerror_handler(), the value of the SMMU_GERROR register is |
| filtered by GERROR_ERR_MASK. However, the GERROR_ERR_MASK does not contain |
| the SFM bit. As a result, the subsequent error processing is not performed |
| when only the SFM error occurs. |
| |
| Fixes: 48ec83bcbcf5 ("iommu/arm-smmu: Add initial driver support for ARM SMMUv3 devices") |
| Reported-by: Rui Zhu <zhurui3@huawei.com> |
| Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> |
| Link: https://lore.kernel.org/r/20210324081603.1074-1-thunder.leizhen@huawei.com |
| Signed-off-by: Will Deacon <will@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |
| index 96c2e9565e00..190f723a5bcd 100644 |
| --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |
| +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |
| @@ -115,7 +115,7 @@ |
| #define GERROR_PRIQ_ABT_ERR (1 << 3) |
| #define GERROR_EVTQ_ABT_ERR (1 << 2) |
| #define GERROR_CMDQ_ERR (1 << 0) |
| -#define GERROR_ERR_MASK 0xfd |
| +#define GERROR_ERR_MASK 0x1fd |
| |
| #define ARM_SMMU_GERRORN 0x64 |
| |
| -- |
| 2.30.2 |
| |
