| From ed1531e4a8650a5933b70c90a941fa8a54bb31a6 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 2 Mar 2021 11:54:12 +0100 |
| Subject: phy: ralink: phy-mt7621-pci: fix XTAL bitmask |
| |
| From: Sergio Paracuellos <sergio.paracuellos@gmail.com> |
| |
| [ Upstream commit 982313c38f2f3793b6435ff50997ae96a2274f5a ] |
| |
| When this was rewriten to get mainlined and start to |
| use 'linux/bitfield.h' headers, XTAL_MASK was wrong. |
| It must mask three bits but only two were used. Hence |
| properly fix it to make things work. |
| |
| Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") |
| Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> |
| Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com |
| Signed-off-by: Vinod Koul <vkoul@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/phy/ralink/phy-mt7621-pci.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c |
| index 9a610b414b1f..84ee2b5c2228 100644 |
| --- a/drivers/phy/ralink/phy-mt7621-pci.c |
| +++ b/drivers/phy/ralink/phy-mt7621-pci.c |
| @@ -62,7 +62,7 @@ |
| |
| #define RG_PE1_FRC_MSTCKDIV BIT(5) |
| |
| -#define XTAL_MASK GENMASK(7, 6) |
| +#define XTAL_MASK GENMASK(8, 6) |
| |
| #define MAX_PHYS 2 |
| |
| -- |
| 2.30.2 |
| |
