| From f3a8076eb28cae1553958c629aecec479394bbe2 Mon Sep 17 00:00:00 2001 |
| From: Le Ma <le.ma@amd.com> |
| Date: Sat, 4 Dec 2021 18:59:08 +0800 |
| Subject: drm/amdgpu: correct register access for RLC_JUMP_TABLE_RESTORE |
| |
| From: Le Ma <le.ma@amd.com> |
| |
| commit f3a8076eb28cae1553958c629aecec479394bbe2 upstream. |
| |
| should count on GC IP base address |
| |
| Signed-off-by: Le Ma <le.ma@amd.com> |
| Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> |
| Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |
| @@ -3061,8 +3061,8 @@ static void gfx_v9_0_init_pg(struct amdg |
| AMD_PG_SUPPORT_CP | |
| AMD_PG_SUPPORT_GDS | |
| AMD_PG_SUPPORT_RLC_SMU_HS)) { |
| - WREG32(mmRLC_JUMP_TABLE_RESTORE, |
| - adev->gfx.rlc.cp_table_gpu_addr >> 8); |
| + WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, |
| + adev->gfx.rlc.cp_table_gpu_addr >> 8); |
| gfx_v9_0_init_gfx_power_gating(adev); |
| } |
| } |
