| From afd55e6d1bd35b4b36847869011447a83a81c8e0 Mon Sep 17 00:00:00 2001 |
| From: Sivaprakash Murugesan <sivaprak@codeaurora.org> |
| Date: Wed, 29 Jul 2020 21:00:03 +0530 |
| Subject: phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init |
| |
| From: Sivaprakash Murugesan <sivaprak@codeaurora.org> |
| |
| commit afd55e6d1bd35b4b36847869011447a83a81c8e0 upstream. |
| |
| There were some problem in ipq8074 Gen2 PCIe phy init sequence. |
| |
| 1. Few register values were wrongly updated in the phy init sequence. |
| 2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter |
| register which is added in serdes table causing the wrong register |
| was getting updated. |
| 3. Clocks and resets were not added in the phy init. |
| |
| Fix these to make Gen2 PCIe port on ipq8074 devices to work. |
| |
| Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074") |
| Cc: stable@vger.kernel.org |
| Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> |
| Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> |
| Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> |
| Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.org |
| Signed-off-by: Vinod Koul <vkoul@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/phy/qualcomm/phy-qcom-qmp.c | 16 +++++++++------- |
| drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ |
| 2 files changed, 11 insertions(+), 7 deletions(-) |
| |
| --- a/drivers/phy/qualcomm/phy-qcom-qmp.c |
| +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c |
| @@ -402,8 +402,8 @@ static const struct qmp_phy_init_tbl ipq |
| QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), |
| QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), |
| - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f), |
| - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), |
| + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), |
| + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), |
| QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), |
| QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), |
| @@ -429,7 +429,6 @@ static const struct qmp_phy_init_tbl ipq |
| QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), |
| QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), |
| QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), |
| - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), |
| @@ -438,7 +437,6 @@ static const struct qmp_phy_init_tbl ipq |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), |
| QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), |
| QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), |
| - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { |
| @@ -446,6 +444,8 @@ static const struct qmp_phy_init_tbl ipq |
| QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), |
| QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), |
| QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), |
| + QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), |
| + QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { |
| @@ -456,7 +456,6 @@ static const struct qmp_phy_init_tbl ipq |
| QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), |
| QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), |
| QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), |
| - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), |
| }; |
| |
| static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { |
| @@ -1107,6 +1106,9 @@ static const struct qmp_phy_cfg msm8996_ |
| .pwrdn_ctrl = SW_PWRDN, |
| }; |
| |
| +static const char * const ipq8074_pciephy_clk_l[] = { |
| + "aux", "cfg_ahb", |
| +}; |
| /* list of resets */ |
| static const char * const ipq8074_pciephy_reset_l[] = { |
| "phy", "common", |
| @@ -1124,8 +1126,8 @@ static const struct qmp_phy_cfg ipq8074_ |
| .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), |
| .pcs_tbl = ipq8074_pcie_pcs_tbl, |
| .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), |
| - .clk_list = NULL, |
| - .num_clks = 0, |
| + .clk_list = ipq8074_pciephy_clk_l, |
| + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), |
| .reset_list = ipq8074_pciephy_reset_l, |
| .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), |
| .vreg_list = NULL, |
| --- a/drivers/phy/qualcomm/phy-qcom-qmp.h |
| +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h |
| @@ -77,6 +77,8 @@ |
| #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc |
| |
| /* Only for QMP V2 PHY - TX registers */ |
| +#define QSERDES_TX_EMP_POST1_LVL 0x018 |
| +#define QSERDES_TX_SLEW_CNTL 0x040 |
| #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 |
| #define QSERDES_TX_DEBUG_BUS_SEL 0x064 |
| #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 |